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preliminary ds-lm3s817-02 copyright ? 2007 luminary micro, inc. lm3s817 microcontroller data sheet
2 may 4, 2007 preliminary legal disclaimers and trademark information information in this document is provided in connection with luminary micro products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in luminary micro?s terms and conditions of sale for such products, luminary micro assumes no liability whatsoever, and luminary micro disclaims any express or implied warranty, relating to sale and/or use of luminary micro?s products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. luminary micro?s products are not intended for use in medical, life saving, or life-sustaining applications. luminary micro may make changes to specifications and product descriptions at any time, w ithout notice. contact your local lumi nary micro sales office or your distributor to obtain the latest spec ifications before pl acing your product order. designers must not rely on the ab sence or characteri stics of any features or instructions marked "reserved" or "undefined." lum inary micro reserves these for future definition and sh all have no responsibility whatsoever for c onflicts or incompatibilities arising fro m future changes to them. copyright ? 2007 luminary micro, inc. all ri ghts reserved. stellaris is a registered tr ademark and the luminary micro logo is a trademark of luminary micro, inc. or its subsidiaries in the united states and ot her countries. arm and thumb ar e registered trademarks, and cortex is a trademark of arm limited. othe r names and brands may be clai med as the property of others. luminary micro, inc. 108 wild basin, suite 350 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www.luminarymicro.com
lm3s817 data sheet may 4, 2007 3 preliminary table of contents legal disclaimers and trademark information.............................................................................. 2 revision history ............................................................................................................... .............. 17 about this document............................................................................................................ ......... 18 audience....................................................................................................................... .................................... 18 about this manual.............................................................................................................. .............................. 18 related documents .............................................................................................................. ............................ 18 documentation conventions...................................................................................................... ....................... 18 1. architectural overview ....................................................................................................... 21 1.1 product features ............................................................................................................ ..................... 21 1.2 target applications ......................................................................................................... ..................... 25 1.3 high-level block diagr am .................................................................................................... ............... 26 1.4 functional overview ......................................................................................................... ................... 27 1.4.1 arm cortex?-m3 ............................................................................................................ ................... 27 1.4.2 motor control peripherals ................................................................................................. ................... 27 1.4.3 analog peripherals ........................................................................................................ ...................... 28 1.4.4 serial communications peripherals......................................................................................... ............ 28 1.4.5 system peripherals........................................................................................................ ...................... 29 1.4.6 memory peripherals........................................................................................................ ..................... 30 1.4.7 additional features ....................................................................................................... ....................... 30 1.4.8 hardware details .......................................................................................................... ....................... 31 1.5 system block diagram ........................................................................................................ ................ 32 2. arm cortex-m3 processor core........................................................................................ 33 2.1 block diagram ............................................................................................................... ...................... 34 2.2 functional description ...................................................................................................... ................... 34 2.2.1 serial wire and jtag debu g ................................................................................................ .............. 34 2.2.2 embedded trace macrocell (etm) ............................................................................................ .......... 35 2.2.3 trace port interface unit (tpiu) .......................................................................................... ................ 35 2.2.4 rom table ................................................................................................................. ......................... 35 2.2.5 memory protection unit (mpu) .............................................................................................. .............. 35 2.2.6 nested vectored interrupt controller (nvic) ... ............................................................................ ........ 35 3. memory map ................................................................................................................... ..... 41 4. interrupts ................................................................................................................... .......... 43 5. jtag interface ............................................................................................................... ..... 46 5.1 block diagram ............................................................................................................... ...................... 47 5.2 functional description ...................................................................................................... ................... 47 5.2.1 jtag interface pins....................................................................................................... ...................... 48 5.2.2 jtag tap controller ....................................................................................................... .................... 49 5.2.3 shift registers ........................................................................................................... .......................... 50 5.2.4 operational considerations ................................................................................................ ................. 50 5.3 initialization and configuration............................................................................................ ................. 51 5.4 register descriptions....................................................................................................... .................... 52 5.4.1 instruction register (ir) ................................................................................................. ...................... 52 5.4.2 data registers ............................................................................................................ ......................... 54
table of contents 4 may 4, 2007 preliminary 6. system control............................................................................................................... ..... 56 6.1 functional description ...................................................................................................... ................... 56 6.1.1 device identification..................................................................................................... ........................ 56 6.1.2 reset control ............................................................................................................. .......................... 56 6.1.3 power control ............................................................................................................. ......................... 59 6.1.4 clock control ............................................................................................................. .......................... 59 6.1.5 system control ............................................................................................................ ........................ 61 6.2 initialization and configuration............................................................................................ ................. 62 6.3 register map ................................................................................................................ ....................... 62 6.4 register descriptions....................................................................................................... .................... 63 7. internal memory .............................................................................................................. .... 98 7.1 block diagram ............................................................................................................... ...................... 98 7.2 functional description ...................................................................................................... ................... 98 7.2.1 sram memory ............................................................................................................... ..................... 98 7.2.2 flash memory .............................................................................................................. ........................ 99 7.3 initialization and configuration............................................................................................ ............... 101 7.3.1 changing flash protection bits ............................................................................................ ............. 101 7.3.2 flash programming ......................................................................................................... .................. 102 7.4 register map ................................................................................................................ ..................... 102 7.5 register descriptions....................................................................................................... .................. 103 8. general-purpose input/outputs (gpios) ........................................................................ 115 8.1 block diagram ............................................................................................................... .................... 116 8.2 functional description ...................................................................................................... ................. 116 8.2.1 data register operation ................................................................................................... ................. 117 8.2.2 data direction ............................................................................................................ ........................ 118 8.2.3 interrupt operation....................................................................................................... ...................... 118 8.2.4 mode control .............................................................................................................. ....................... 119 8.2.5 pad configuration ......................................................................................................... ..................... 119 8.2.6 identification............................................................................................................ ........................... 119 8.3 initialization and configuration............................................................................................ ............... 119 8.4 register map ................................................................................................................ ..................... 121 8.5 register descriptions....................................................................................................... .................. 122 9. general-purpose timers .................................................................................................. 153 9.1 block diagram ............................................................................................................... .................... 154 9.2 functional description ...................................................................................................... ................. 154 9.2.1 gptm reset conditions ..................................................................................................... ............... 154 9.2.2 32-bit timer operating modes.............................................................................................. ............. 154 9.2.3 16-bit timer operating modes.............................................................................................. ............. 156 9.3 initialization and configuration............................................................................................ ............... 160 9.3.1 32-bit one-shot/periodic timer mode .......... ............................................................................. ........ 160 9.3.2 32-bit real-time clock (rtc) mode ............... .......................................................................... ........ 161 9.3.3 16-bit one-shot/periodic timer mode .......... ............................................................................. ........ 161 9.3.4 16-bit input edge count mode .............................................................................................. ............ 161 9.3.5 16-bit input edge timing mode ................. ............................................................................ ............ 162 9.3.6 16-bit pwm mode........................................................................................................... ................... 162 9.4 register map ................................................................................................................ ..................... 163 9.5 register descriptions....................................................................................................... .................. 164
lm3s817 data sheet may 4, 2007 5 preliminary 10. watchdog timer .............................................................................................................. .. 185 10.1 block diagram .............................................................................................................. ..................... 185 10.2 functional description ..................................................................................................... .................. 186 10.3 initialization and configuration........................................................................................... ................ 186 10.4 register map ............................................................................................................... ...................... 186 10.5 register descriptions...................................................................................................... ................... 187 11. analog-to-digital converter (adc) .................................................................................. 208 11.1 block diagram .............................................................................................................. ..................... 209 11.2 functional description ..................................................................................................... .................. 209 11.2.1 sample sequ encers ........................................................................................................ .................. 209 11.2.2 module control ........................................................................................................... ....................... 210 11.2.3 hardware samp le averaging circuit........................................................................................ .......... 211 11.2.4 analog-to-digital converter .............................................................................................. ................. 211 11.2.5 test modes ............................................................................................................... ......................... 211 11.2.6 internal temp erature sensor .............................................................................................. ............... 211 11.3 initialization and configuration........................................................................................... ................ 211 11.3.1 module initialization .................................................................................................... ....................... 212 11.3.2 sample se quencer configuration ........ ................................................................................... ........... 212 11.4 register map ............................................................................................................... ...................... 212 11.5 register descriptions...................................................................................................... ................... 213 12. universal asynchronous receivers/transmitters (uarts).......................................... 238 12.1 block diagram .............................................................................................................. ..................... 239 12.2 functional description ..................................................................................................... .................. 239 12.2.1 transmit/receive logic ................................................................................................... .................. 239 12.2.2 baud-rate generation ..... ................................................................................................ .................. 240 12.2.3 data transmission ........................................................................................................ ..................... 241 12.2.4 fifo operation ........................................................................................................... ....................... 241 12.2.5 interrupts ............................................................................................................... ............................. 241 12.2.6 loopback operation ....................................................................................................... ................... 242 12.3 initialization and configuration........................................................................................... ................ 242 12.4 register map ............................................................................................................... ...................... 243 12.5 register descriptions...................................................................................................... ................... 244 13. synchronous serial interface (ssi) ................................................................................. 274 13.1 block diagram .............................................................................................................. ..................... 274 13.2 functional description ..................................................................................................... .................. 275 13.2.1 bit rate generation ...................................................................................................... ..................... 275 13.2.2 fifo operation ........................................................................................................... ....................... 275 13.2.3 interrupts ............................................................................................................... ............................. 275 13.2.4 frame formats ............................................................................................................ ...................... 276 13.3 initialization and configuration........................................................................................... ................ 283 13.4 register map ............................................................................................................... ...................... 284 13.5 register descriptions...................................................................................................... ................... 285 14. analog comparator........................................................................................................... 309 14.1 block diagram .............................................................................................................. ..................... 309 14.2 functional description ..................................................................................................... .................. 309 14.2.1 internal refe rence programming........................................................................................... ............ 310 14.3 initialization and configuration........................................................................................... ................ 311
table of contents 6 may 4, 2007 preliminary 14.4 register map ............................................................................................................... ...................... 312 14.5 register descriptions...................................................................................................... ................... 312 15. pulse width modulator (pwm) ......................................................................................... 320 15.1 block diagram .............................................................................................................. ..................... 320 15.2 functional description ..................................................................................................... .................. 320 15.2.1 pwm timer ................................................................................................................ ........................ 320 15.2.2 pwm comparators ............. ............................................................................................. .................. 320 15.2.3 pwm signal generator ....... .............................................................................................. ................. 321 15.2.4 dead-band generator ..... ................................................................................................. ................. 322 15.2.5 interrupt se lector ....................................................................................................... ........................ 322 15.2.6 synchronization methods .......................... ........................................................................ ................ 322 15.2.7 fault conditions ......................................................................................................... ........................ 323 15.2.8 output control block..................................................................................................... ..................... 323 15.3 initialization and configuration........................................................................................... ................ 323 15.4 register map ............................................................................................................... ...................... 324 15.5 register descriptions...................................................................................................... ................... 325 16. pin diagram ................................................................................................................. ...... 349 17. signal tables ............................................................................................................... ...... 350 18. operating characteristics ................................................................................................ 360 19. electrical characteristics ................................................................................................. 3 61 19.1 dc characteristics ......................................................................................................... .................... 361 19.1.1 maximum ratings .......................................................................................................... .................... 361 19.1.2 recommended dc operating c onditions ...................................................................................... ... 361 19.1.3 on-chip low drop-out (ldo) r egulator characteristics .................................................................. 362 19.1.4 power specifications ..................................................................................................... .................... 363 19.1.5 flash memory characteristics ............................................................................................. .............. 364 19.2 ac characteristics ......................................................................................................... .................... 364 19.2.1 load conditions .......................................................................................................... ....................... 364 19.2.2 clocks ................................................................................................................... ............................. 364 19.2.3 analog-to-digital converter .............................................................................................. ................. 365 19.2.4 analog comparator........................................................................................................ .................... 366 19.2.5 synchronous serial interface (ssi) ....................................................................................... ............ 366 19.2.6 jtag and boundary scan ................................................................................................... .............. 368 19.2.7 general-purpose i/o..... ................................................................................................. .................... 370 19.2.8 reset .................................................................................................................... ............................. 370 20. package information......................................................................................................... 373 appendix a. serial flash loader ............................................................................................... 37 4 21.1 interfaces ................................................................................................................. .......................... 374 21.1.1 uart ..................................................................................................................... ............................ 374 21.1.2 ssi ...................................................................................................................... ............................... 374 21.2 packet handling............................................................................................................ ..................... 374 21.2.1 packet format .... ........................................................................................................ ....................... 375 21.2.2 sending packets .............. ............................................................................................ ...................... 375 21.2.3 receiving packets ........................................................................................................ ..................... 375 21.3 commands ................................................................................................................... ..................... 375 21.3.1 command_ping (0x20) ...................................................................................................... ............ 376 21.3.2 command_get_status (0x23) ................................................................................................ ... 376 21.3.3 command_download (0x21). ................................................................................................. .... 376 21.3.4 command_send_data (0x24) ................................................................................................. .... 376
lm3s817 data sheet may 4, 2007 7 preliminary 21.3.5 command_run (0x22) ........ ............................................................................................... ............ 377 21.3.6 command_reset (0x25)....... ................ ................ ................ ................ ................. ............. .......... 377 ordering and contact information .............................................................................................. 3 79 ordering information.. ......................................................................................................... ............................ 379 development kit ................................................................................................................ ............................. 379 company information ................ ............................................................................................ ......................... 379 support information ............................................................................................................ ............................ 380
list of figures 8 may 4, 2007 preliminary list of figures figure 1-1. stellaris ? high-level block diagram ...................................................................................... 26 figure 1-2. lm3s817 controller system-level block di agram ................................................................... 32 figure 2-1. cpu block diagram ........................... ........................................................................ ............... 34 figure 2-2. tpiu block diagram ................................................................................................... ............... 35 figure 5-1. jtag module block diagram ............................................................................................ ........ 47 figure 5-2. test access port state machine ....................................................................................... ........ 50 figure 5-3. idcode register format...................... ......................................................................... ........... 54 figure 5-4. bypass register format .. ................ ................ ................. ................ ................ ............ .......... 54 figure 5-5. boundary scan register format ........................................................................................ ....... 55 figure 6-1. external circuitry to extend reset................................................................................... .......... 57 figure 6-2. main clock tree ...................................................................................................... .................. 60 figure 7-1. flash block diagram .................................................................................................. ............... 98 figure 8-1. gpio module block diagram .................... ........................................................................ ...... 116 figure 8-2. gpio port block diagram.............................................................................................. .......... 117 figure 8-3. gpiodata write example............................................................................................... ....... 118 figure 8-4. gpiodata read example ................................................................................................ ..... 118 figure 9-1. gptm module block dia gram ............................................................................................ ..... 154 figure 9-2. 16-bit input edge count mode example ... .............................................................................. 158 figure 9-3. 16-bit input edge time mode example.................................................................................. . 159 figure 9-4. 16-bit pwm mode example .............................................................................................. ...... 160 figure 10-1. wdt module block dia gram ............................................................................................ ....... 185 figure 11-1. adc module block diagram.................. .......................................................................... ........ 209 figure 11-2. internal temperature se nsor characteristic.......................................................................... .. 211 figure 12-1. uart module block dia gram........................................................................................... ....... 239 figure 12-2. uart character frame................................................................................................ ........... 240 figure 13-1. ssi module block diagram................. ........................................................................... .......... 274 figure 13-2. ti synchronous serial fr ame format (single transfer).......................................................... 276 figure 13-3. ti synchronous serial frame format (con tinuous transfer) ................................................. 277 figure 13-4. freescale spi format (single transfer ) with spo=0 and sph=0 .......................................... 278 figure 13-5. freescale spi format (continuous transfer) with spo=0 and sph=0 .................................. 278 figure 13-6. freescale spi frame format with spo=0 and sph=1........................................................... 279 figure 13-7. freescale spi frame fo rmat (single transfer) with spo=1 and sph=0............................... 279 figure 13-8. freescale spi frame fo rmat (continuous transfer) with spo=1 and sph=0....................... 280 figure 13-9. freescale spi frame format with spo=1 and sph=1........................................................... 280 figure 13-10. microwire frame format (single frame)... ........................................................................ 281 figure 13-11. microwire frame format (continuous transfer) ............................................................... 282 figure 13-12. microwire frame format, ssifss input setup and hold requirements............................ 283 figure 14-1. analog comparator modu le block diagram ............................................................................ 30 9 figure 14-2. structure of comparator unit........................................................................................ ........... 310 figure 14-3. comparator internal reference structure ............................................................................. .. 311 figure 15-1. pwm module block di agram............................................................................................ ....... 320 figure 15-2. pwm count-down mode ................................................................................................. ........ 321 figure 15-3. pwm count-up/down mo de .............................................................................................. ..... 321 figure 15-4. pwm generation example in count-up/dow n mode ............................................................. 322 figure 15-5. pwm dead-band generator ............................................................................................. ...... 322 figure 16-1. pin connection diagram ........................................................................................... ............ 349
lm3s817 data sheet may 4, 2007 9 preliminary figure 19-1. load conditions..... ................................................................................................ .................. 364 figure 19-2. ssi timing for ti frame format (frf=0 1), single transfer timing measurement ................ 367 figure 19-3. ssi timing for microwire frame format (frf=10), single transfer ................................. 367 figure 19-4. ssi timing for spi frame format (frf= 00), with sph=1...................................................... 367 figure 19-5. jtag test clock input timing........................................................................................ ......... 369 figure 19-6. jtag test access port (tap) timing .................................................................................. ... 369 figure 19-7. jtag trst timing ................................................................................................................. 369 figure 19-8. external reset timing (rst )................................................................................................... 371 figure 19-9. power-on reset timing ..................... .......................................................................... ........... 371 figure 19-10. brown-out reset timing ............................................................................................. ............ 371 figure 19-11. software reset timing .................... .......................................................................... .............. 371 figure 19-12. watchdog reset timing ..................... ......................................................................... ............ 372 figure 19-13. ldo reset timing ................................................................................................... ................ 372 figure 20-1. 48-pin lqfp package........................ ......................................................................... ............ 373
list of tables 10 may 4, 2007 preliminary list of tables table 0-1. documentation conventions ............................................................................................. ........ 18 table 3-1. memory map............................................................................................................ .................. 41 table 4-1. exception types ....................................................................................................... ................. 43 table 4-2. interrupts ............................................................................................................ ....................... 44 table 5-1. jtag port pins reset state ............................................................................................ .......... 48 table 5-2. jtag instruction register commands .................................................................................... .. 52 table 6-1. system control register map........................................................................................... ......... 62 table 6-2. vadj to vout .......................................................................................................... ................ 75 table 6-3. pll mode control...................................................................................................... ................ 87 table 6-4. default crystal field values and pll programming ................................................................. 88 table 7-1. flash protection policy combinations .................................................................................. ... 100 table 7-2. flash register map .................................................................................................... ............. 103 table 8-1. gpio pad configuration examples ....................................................................................... . 120 table 8-2. gpio interrupt configur ation example .................................................................................. . 120 table 8-3. gpio register map ..................................................................................................... ............ 121 table 9-1. 16-bit timer with prescale r configurations ............................................................................ . 157 table 9-2. gptm register map..................................................................................................... ........... 163 table 10-1. wdt register map ..................................................................................................... ............. 186 table 11-1. samples and fifo depth of sequencers................................................................................ 2 09 table 11-2. adc register map..................................................................................................... .............. 212 table 12-1. uart register map .................................................................................................... ............ 243 table 13-1. ssi register map ..................................................................................................... ............... 284 table 14-1. comparator 0 operating modes ......................................................................................... ..... 310 table 14-2. internal reference volt age and acrefctl field values ...................................................... 311 table 14-3. analog comparator register map ....................................................................................... .... 312 table 15-1. pwm register map ..................................................................................................... ............ 324 table 15-2. pwm generator action encodings....................................................................................... ... 344 table 17-1. signals by pin number ................................................................................................ ............ 350 table 17-2. signals by signal name ............................................................................................... ........... 353 table 17-3. signals by function, except for gpio ................................................................................. .... 355 table 17-4. gpio pins and alternate functions.................................................................................... ..... 358 table 18-1. temperature characteristics ................. ......................................................................... ......... 360 table 18-2. thermal characteristics.............................................................................................. ............. 360 table 19-1. maximum ratings...................................................................................................... .............. 361 table 19-2. recommended dc operating conditions ............................................................................... 361 table 19-3. ldo regulator characteristics........................................................................................ ........ 362 table 19-4. power specifications ................................................................................................. .............. 363 table 19-5. flash memory characteristics ......................................................................................... ........ 364 table 19-6. phase locked loop (pll) characteristics .............................................................................. 364 table 19-7. clock characteristics................................................................................................ ............... 365 table 19-8. adc characteristics .................................................................................................. .............. 365 table 19-9. analog comparator characteristics.................................................................................... ..... 366 table 19-10. analog com parator voltage reference characteristics.......................................................... 366 table 19-11. ssi characteristics ................................................................................................. ................. 366 table 19-12. jtag characteristics................................................................................................ ............... 368 table 19-13. gpio characteristics................................................................................................ ............... 370 table 19-14. reset characteristics ............................................................................................... ............... 370
lm3s817 data sheet may 4, 2007 11 preliminary list of registers arm cortex-m3 processor core ................................................................................................... 33 register 1: systick control and status register.................................................................................. ....... 38 register 2: systick reload value register .......... .............................................................................. ......... 39 register 3: systick current value register ....................................................................................... ......... 40 system control ................................................................................................................. .............. 56 register 1: device identification 0 (did0), offset 0x000 ......................................................................... ..... 64 register 2: device identification 1 (did1), offset 0x004 ......................................................................... ..... 65 register 3: device capabilities 0 ( dc0), offset 0x008............................................................................ ..... 67 register 4: device capabilities 1 ( dc1), offset 0x010............................................................................ ..... 68 register 5: device capabilities 2 ( dc2), offset 0x014............................................................................ ..... 70 register 6: device capabilities 3 ( dc3), offset 0x018............................................................................ ..... 71 register 7: device capabilities 4 ( dc4), offset 0x01c ............................................................................ .... 73 register 8: power-on and brown-out reset control (pborctl), offset 0x030 ........................................ 74 register 9: ldo power control (ldopctl), offset 0x03 4.......................................................................... 75 register 10: software reset control 0 (srcr0), offset 0x 040 ..................................................................... 7 6 register 11: software reset control 1 (srcr1), offset 0x 044 ..................................................................... 7 7 register 12: software reset control 2 (srcr2), offset 0x 048 ..................................................................... 7 8 register 13: raw interrupt status (ris), offset 0x050............................................................................ ....... 79 register 14: interrupt mask co ntrol (imc), offset 0x054 .......................................................................... ..... 80 register 15: masked interrupt status and clear (misc), offset 0x058.......................................................... 82 register 16: reset cause (resc), offset 0x05c .................................................................................... ...... 83 register 17: run-mode clock co nfiguration (rcc), offset 0x060................................................................. 84 register 18: xtal to pll translation (pllcfg), offset 0x064 .................................................................... 89 register 19: run-mode clock gating control 0 (rcgc0), offset 0x100 ....................................................... 90 register 20: sleep-mode clock gating control 0 (scgc0), offset 0x110..................................................... 90 register 21: deep-sleep-mode clock gati ng control 0 (dcgc0), offset 0x120........................................... 90 register 22: run-mode clock gating control 1 (rcgc1), offset 0x104 ....................................................... 92 register 23: sleep-mode clock gating control 1 (scgc1), offset 0x114..................................................... 92 register 24: deep-sleep-mode clock gati ng control 1 (dcgc1), offset 0x124........................................... 92 register 25: run-mode clock gating control 2 (rcgc2), offset 0x108 ....................................................... 94 register 26: sleep-mode clock gating control 2 (scgc2), offset 0x118..................................................... 94 register 27: deep-sleep-mode clock gati ng control 2 (dcgc2), offset 0x128........................................... 94 register 28: deep-sleep clock configuration (dslpclkcf g), offset 0x144 .............................................. 95 register 29: clock verification clear (clkvclr), offset 0x150.................................................................... 96 register 30: allow unregulated ldo to reset the part (ldoarst), offset 0x160 ....................................... 97 internal memory ................................................................................................................ .............. 98 register 1: flash memory protection read enable (fmp re), offset 0x130 ............................................. 104 register 2: flash memory protection program enable (fmppe), offset 0x134 ........................................ 105 register 3: usec reload (usecrl), offset 0x140................................................................................... . 106 register 4: flash memory address (fma), offset 0x00 0 ........................................................................... 10 7 register 5: flash memory data (fmd), offset 0x004 ................................................................................ 109 register 6: flash memory control (fmc), offset 0x008 ............................................................................ 1 10 register 7: flash controller raw interrupt status (fcri s), offset 0x00c ................................................. 112 register 8: flash controller interrupt mask (fcim), offset 0x010 ............................................................. 113 register 9: flash controller masked interrupt status and clear (fcmisc), offset 0x014......................... 114
list of registers 12 may 4, 2007 preliminary general-purpose input/outputs (gpios) .................................................................................... 115 register 1: gpio data (gpiodata), offset 0x000 ........ ........................................................................... 123 register 2: gpio direction (gpiodir), offset 0x400 ............................................................................... . 124 register 3: gpio interrupt sense (gpi ois), offset 0x404........ ................ ............. ............. ............ ........... 1 25 register 4: gpio interrupt both edge s (gpioibe), offset 0x408.............................................................. 126 register 5: gpio interrupt event (gpi oiev), offset 0x40c....................................................................... 12 7 register 6: gpio interrupt mask (gpioi m), offset 0x410.......................................................................... 1 28 register 7: gpio raw interrupt status (gpioris), offset 0x414.............................................................. 129 register 8: gpio masked interrupt status (gpiomis), offset 0x418 ........................................................ 130 register 9: gpio interrupt clear (gpi oicr), offset 0x41c....................................................................... 13 1 register 10: gpio alternate function select (gpioafsel), offset 0x420 ................................................. 132 register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500.............................................................. 133 register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504.............................................................. 134 register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508.............................................................. 135 register 14: gpio open drain select (gpioodr), offset 0x50c............................................................... 136 register 15: gpio pull-up select (gpiopur), offset 0x 510 ...................................................................... 137 register 16: gpio pull-down select (g piopdr), offset 0x514.................................................................. 138 register 17: gpio slew rate control select (gpioslr), offset 0x518...................................................... 139 register 18: gpio digital input enable (gpioden), offset 0x51c ............................................................. 140 register 19: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 ........................................... 141 register 20: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 ........................................... 142 register 21: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 ........................................... 143 register 22: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc........................................... 144 register 23: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 ........................................... 145 register 24: gpio peripheral identification 1(gpioperi phid1), offset 0xfe4 ............................................ 146 register 25: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 ........................................... 147 register 26: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec........................................... 148 register 27: gpio primecell identification 0 (gpiopcelli d0), offset 0xff0 .............................................. 149 register 28: gpio primecell identification 1 (gpiopcelli d1), offset 0xff4 .............................................. 150 register 29: gpio primecell identification 2 (gpiopcelli d2), offset 0xff8 .............................................. 151 register 30: gpio primecell identification 3 (gpiopcelli d3), offset 0xffc.............................................. 152 general-purpose timers ......................................................................................................... ..... 153 register 1: gptm configuration (gptmcfg), offset 0x 000..................................................................... 165 register 2: gptm timera mode (gpt mtamr), offset 0x004 .................................................................. 166 register 3: gptm timerb mode (gpt mtbmr), offset 0x008 .................................................................. 167 register 4: gptm control (gptmctl), offset 0x00c............................................................................... 16 8 register 5: gptm interrupt mask (gptmimr), offset 0x018 .................................................................... 170 register 6: gptm raw interrupt stat us (gptmris), offset 0x01c .......................................................... 172 register 7: gptm masked interrupt st atus (gptmmis), offset 0x020 ..................................................... 173 register 8: gptm interrupt clear (gptmicr), offset 0x024..................................................................... 174 register 9: gptm timera interval load (gptmtailr), offset 0x028 ...................................................... 175 register 10: gptm timerb interval load (gptmtbilr), offset 0x02c...................................................... 176 register 11: gptm timera match (gptmtamatchr), offs et 0x030 ....................................................... 177 register 12: gptm timerb match (gptmtbmatchr), offs et 0x034 ....................................................... 178 register 13: gptm timera prescale (gptmtapr), offset 0x038.............................................................. 179 register 14: gptm timerb prescale (gptmtbpr), offset 0x03c ............................................................. 180
lm3s817 data sheet may 4, 2007 13 preliminary register 15: gptm timera prescale match (gptmtapmr), offset 0x040................................................ 181 register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044................................................ 182 register 17: gptm timera (gptmtar), offset 0x048 ............................................................................... 18 3 register 18: gptm timerb (gptmtbr), offset 0x04c .............................................................................. 184 watchdog timer................................................................................................................. ........... 185 register 1: watchdog load (wdtload), offset 0x000 ............................................................................ 188 register 2: watchdog value (wdtvalue), offset 0x004 ......................................................................... 189 register 3: watchdog control (wdtctl), offset 0x008. ........................................................................... 19 0 register 4: watchdog interrupt clear (wdticr), offset 0x00c ................................................................ 191 register 5: watchdog raw interrupt status (wdtris), of fset 0x010 ....................................................... 192 register 6: watchdog masked interrupt status (wdtmis) , offset 0x014.................................................. 193 register 7: watchdog lock (wdtlock), offset 0xc00 ............................................................................ 194 register 8: watchdog test (wdttest), offset 0x418 ... ........................................................................... 19 5 register 9: watchdog periphera l identification 4 (wdtperiphid4), offset 0xfd0..................................... 196 register 10: watchdog periphera l identification 5 (wdtperiphid5), offset 0xfd4..................................... 197 register 11: watchdog periphera l identification 6 (wdtperiphid6), offset 0xfd8..................................... 198 register 12: watchdog periphera l identification 7 (wdtperiphid7), offset 0xfdc .................................... 199 register 13: watchdog periphera l identification 0 (wdtperiphid0), offset 0xfe0 ..................................... 200 register 14: watchdog periphera l identification 1 (wdtperiphid1), offset 0xfe4 ..................................... 201 register 15: watchdog periphera l identification 2 (wdtperiphid2), offset 0xfe8 ..................................... 202 register 16: watchdog periphera l identification 3 (wdtperiphid3), offset 0xfec .................................... 203 register 17: watchdog primecell identification 0 (wdtpc ellid0), offset 0xff0........................................ 204 register 18: watchdog primecell identification 1 (wdtpc ellid1), offset 0xff4........................................ 205 register 19: watchdog primecell identification 2 (wdtpc ellid2), offset 0xff8........................................ 206 register 20: watchdog primecell identification 3 (wdtpce llid3 ), offset 0xffc ...................................... 207 analog-to-digital converter (adc).............................................................................................. 208 register 1: adc active sample seque ncer (adcactss), offset 0x000 .................................................. 214 register 2: adc raw interrupt status (adcris), offset 0x004................................................................. 215 register 3: adc interrupt mask (adcim ), offset 0x008 ............................................................................ 2 16 register 4: adc interrupt status and clear (adcisc), offset 0x00c........................................................ 217 register 5: adc overflow status (adcostat), offset 0x010 .................................................................. 218 register 6: adc event multiplexer select (adcemux), offset 0x014 ...................................................... 219 register 7: adc underflow status (adcustat), offset 0x018 ................................................................ 220 register 8: adc sample sequ encer priority (adcsspri), offset 0x020.................................................. 221 register 9: adc processor sample se quence initiate (adcpssi), offset 0x028 ................. ............. ....... 222 register 10: adc sample averaging control (adcsac), o ffset 0x030 ...................................................... 223 register 11: adc sample sequence in put multiplexer select 0 (adcssmux 0), offset 0x040.................. 224 register 12: adc sample sequence control 0 (adcssctl 0), offset 0x044............................................. 226 register 13: adc sample sequence re sult fifo 0 (adcssfifo0), offset 0x048.................................... 228 register 14: adc sample sequence fifo 0 status (a dcssfstat0), offset 0x04c................................ 229 register 15: adc sample sequence in put multiplexer select 1 (adcssmux 1), offset 0x060.................. 230 register 16: adc sample sequence control 1 (adcssctl 1), offset 0x064............................................. 231 register 17: adc sample sequence re sult fifo 1 (adcssfifo1), offset 0x068.................................... 231 register 18: adc sample sequence fifo 1 status (a dcssfstat1), offset 0x06c................................ 231 register 19: adc sample sequence in put multiplexer select 2 (adcssmux 2), offset 0x080.................. 232 register 20: adc sample sequence control 2 (adcssctl 2), offset 0x084............................................. 233
list of registers 14 may 4, 2007 preliminary register 21: adc sample sequence re sult fifo 2 (adcssfifo2), offset 0x088.................................... 233 register 22: adc sample sequence fifo 2 status (a dcssfstat2), offset 0x08c................................ 233 register 23: adc sample sequence in put multiplexer select 3 (adcssmux 3), offset 0x0a0 ................. 234 register 24: adc sample sequence control 3 (adcssctl 3), offset 0x0a4 ............................................ 235 register 25: adc sample sequence re sult fifo 3 (adcssfifo3), offset 0x0a8 ................................... 235 register 26: adc sample sequence fifo 3 status (a dcssfstat3), offset 0x0ac ............................... 235 register 27: adc test mode loopback (adctmlb), offset 0x100 ............................................................ 236 universal asynchronous receivers/transmitters (uarts) ..................................................... 238 register 1: uart data (uartdr), offset 0x000 ........ ............................................................................. . 245 register 2: uart receive status/error clear (uartr sr/uartecr), offset 0x004 .............................. 247 register 3: uart flag (uartfr), offset 0x018 ......... ............................................................................ .. 249 register 4: uart integer baud-rate divisor (uartibrd) , offset 0x024 ................................................. 251 register 5: uart fractional baud-rate divisor (uar tfbrd), offset 0x028 ........................................... 252 register 6: uart line control (uartlcrh), offset 0x 02c ..................................................................... 253 register 7: uart control (uartctl), offset 0x030................................................................................. 255 register 8: uart interrupt fifo level select (uartifls), offset 0x034 ................................................ 256 register 9: uart interrupt mask (uartim), offset 0x 038 ........................................................................ 257 register 10: uart raw interrupt status (uartris), o ffset 0x03c............................................................ 259 register 11: uart masked interrupt st atus (uartmis), offset 0x040 ...................................................... 260 register 12: uart interrupt clear (uarticr), offset 0x044...................................................................... 26 1 register 13: uart peripheral identification 4 (uartperiphid4), offs et 0xfd0.......................................... 262 register 14: uart peripheral identification 5 (uartperiphid5), offs et 0xfd4.......................................... 263 register 15: uart peripheral identification 6 (uartperiphid6), offs et 0xfd8.......................................... 264 register 16: uart peripheral identification 7 (uartperiphid7), offs et 0xfdc ......................................... 265 register 17: uart peripheral identification 0 (uartperiphid0), offs et 0xfe0.......................................... 266 register 18: uart peripheral identification 1 (uartperiphid1), offs et 0xfe4.......................................... 267 register 19: uart peripheral identification 2 (uartperiphid2), offs et 0xfe8.......................................... 268 register 20: uart peripheral identification 3 (uartperiphid3), offs et 0xfec ......................................... 269 register 21: uart primecell identification 0 (uartpce llid0), offset 0xff0............................................. 270 register 22: uart primecell identification 1 (uartpce llid1), offset 0xff4............................................. 271 register 23: uart primecell identification 2 (uartpce llid2), offset 0xff8............................................. 272 register 24: uart primecell identification 3 (uartpce llid3), offset 0xffc ............................................ 273 synchronous serial interface (ssi) ............................................................................................. 274 register 1: ssi control 0 (ssicr0), offset 0x000 ................................................................................. .... 286 register 2: ssi control 1 (ssicr1), offset 0x004 ................................................................................. .... 288 register 3: ssi data (ssidr), offset 0x008 ....................................................................................... ....... 290 register 4: ssi status (ssisr), offset 0x00c ..................................................................................... ...... 291 register 5: ssi clock prescale (ssicpsr), offset 0x010 ......................................................................... 29 2 register 6: ssi interrupt mask (ssiim), offset 0x014 ............................................................................. ... 293 register 7: ssi raw interrupt status (ssiris), offset 0x018 .................................................................... 29 4 register 8: ssi masked interrupt status (ssimis), of fset 0x01c.............................................................. 295 register 9: ssi interrupt clear (ssiicr), offset 0x02 0........................................................................... ... 296 register 10: ssi peripheral i dentification 4 (ssiperiphid4), offset 0xfd0.................................................. 297 register 11: ssi peripheral i dentification 5 (ssiperiphid5), offset 0xfd4.................................................. 298 register 12: ssi peripheral i dentification 6 (ssiperiphid6), offset 0xfd8.................................................. 299 register 13: ssi peripheral i dentification 7 (ssiperiphid7), offset 0xfdc ................................................. 300
lm3s817 data sheet may 4, 2007 15 preliminary register 14: ssi peripheral i dentification 0 (ssiperiphid0), offset 0xfe0.................................................. 301 register 15: ssi peripheral i dentification 1 (ssiperiphid1), offset 0xfe4.................................................. 302 register 16: ssi peripheral i dentification 2 (ssiperiphid2), offset 0xfe8.................................................. 303 register 17: ssi peripheral i dentification 3 (ssiperiphid3), offset 0xfec ................................................. 304 register 18: ssi primecell identificati on 0 (ssipcellid0), offset 0xff0..................................................... 305 register 19: ssi primecell identificati on 1 (ssipcellid1), offset 0xff4..................................................... 306 register 20: ssi primecell identificati on 2 (ssipcellid2), offset 0xff8..................................................... 307 register 21: ssi primecell identificati on 3 (ssipcellid3), offset 0xffc .................................................... 308 analog comparator .............................................................................................................. ........ 309 register 1: analog comparat or masked interrupt status (acmis), of fset 0x00........................................ 313 register 2: analog comparator raw in terrupt status (acris), offset 0x04.............................................. 314 register 3: analog comparator interr upt enable (acinten), offset 0x08 ................................................ 315 register 4: analog comparator refe rence voltage control (acrefctl), offset 0x10 ............................ 316 register 5: analog comparator status 0 (acstat0), offset 0x20 ............................................................ 317 register 6: analog comparator control 0 (acctl0), offset 0x24 ............................................................. 318 pulse width modulator (pwm).................................................................................................... .320 register 1: pwm master control (pwmctl), offset 0x00 0....................................................................... 326 register 2: pwm time base sync (pwmsync), offset 0x004................................................................. 327 register 3: pwm output enable (pwmenable), offset 0x008................................................................ 328 register 4: pwm output inversion (pwminvert), offset 0x00c............................................................. 329 register 5: pwm output fault (pwmfault), offset 0x 010...................................................................... 330 register 6: pwm interrupt enable (pwminten), offset 0x014................................................................. 331 register 7: pwm raw interrupt status (pwmris), offset 0x018 .............................................................. 332 register 8: pwm interrupt status and clear (pwmisc), offset 0x01c ..................................................... 333 register 9: pwm status (pwmstatus), offset 0x020............................................................................. 334 register 10: pwm0 control (pwm0ctl), offset 0x040............................................................................... 3 35 register 11: pwm0 interrupt enable (pwm0inten), offset 0x044............................................................. 336 register 12: pwm0 raw interrupt status (pwm0ris), offset 0x048 .......................................................... 337 register 13: pwm0 interrupt status an d clear (pwm0isc), offset 0x04c ................................................. 338 register 14: pwm0 load (pwm0load), offset 0x050 ............................................................................... 339 register 15: pwm0 counter (pwm0count), offset 0x05 4 ....................................................................... 340 register 16: pwm0 compare a (pwm0cmpa), offset 0x05 8 .................................................................... 341 register 17: pwm0 compare b (pwm0cmpb), offset 0x05 c.................................................................... 342 register 18: pwm0 generator a contro l (pwm0gena), offset 0x060....................................................... 343 register 19: pwm0 generator b contro l (pwm0genb), offset 0x064....................................................... 345 register 20: pwm0 dead-band control (pwm0dbctl), offset 0x068 ...................................................... 346 register 21: pwm0 dead-band rising- edge delay (pwm0dbrise), offset 0x06c .................................. 347 register 22: pwm0 dead-band falling- edge-delay (pwm0dbfall), offset 0x070.................................. 348 pin diagram .................................................................................................................... ............... 349 signal tables.................................................................................................................. ............... 350 operating characteristics ...................................................................................................... ...... 360 electrical characteristics ..................................................................................................... ........ 361 package information ............................................................................................................ ........ 373
lm3s817 data sheet may 4, 2007 17 preliminary revision history this table provides a summary of the document revisions. date revision description february 2007 00 initial release of lm3s317, lm3s617, lm3s618, lm3s817 and lm3s818 data sheet to customers. april 2007 01 second release of lm3s317, lm3s 618, and lm3s817 data sheets. includes the following changes: ? added information to the thermal chapter. ? added information to the power specificat ions section in the electrical chapter. april 2007 02 third release of lm3s317, lm3s 617, lm3s618, lm3s817, and lm3s818 data sheets. includes the following changes: ? in the internal memory chapter, added information on code protection. ? in the arm cortex-m3 processor core, architecture overview, and general-purpose timers chapters, add ed information for the system timer (systick). ? in the timers chapter, added note to the 16-bit input edge time mode section.
about this document 18 may 4, 2007 preliminary about this document this data sheet provides reference information for the lm3s817 microcontroller, describing the functional blocks of the system-on-chip (soc) device designed around the arm? cortex?-m3 core. audience this manual is intended for system software developers, hardware designers, and application developers. about this manual this document is organized into sections that correspond to each major feature. related documents the following documents are referenced by the da ta sheet, and available on the documentation cd or from the luminary micro web site at www.luminarymicro.com: ? arm? cortex?-m3 technical reference manual ? coresight? design kit technical reference manual ? arm? v7-m architecture application level reference manual the following related documents are also referenced: ? ieee standard 1149.1-test access port and boundary-scan architecture this documentation list was current as of public ation date. please check the luminary micro web site for additional documentation, incl uding application notes and white papers. documentation conventions this document uses the conventions shown in table 0-1. table 0-1. documentation conventions notation meaning general register notation register apb registers are indicated in uppercase bold. for example, pborctl is the power-on and brown-out reset control register. if a register name contains a lowercase n, it represents more than one register. for example, srcrn represents any (or all) of the three software reset control registers: srcr0 , srcr1 , and srcr2 . bit a single bit in a register. bit field two or more consecutive and related bits. offset 0x nnn a hexadecimal increment to a regist er?s address, relative to that module?s base address as specified in table 3-1, "memory map," on page 41.
lm3s817 data sheet may 4, 2007 19 preliminary register n registers are numbered consecut ively throughout the document to aid in referencing them. the register number has no meaning to software. reserved register bits marked reserved are reserved for futu re use. reserved bits return an indeterminate value, and should never be changed. only write a reserved bit with its current value. yy : xx the range of register bits inclusive from xx to yy. for example, 31:15 means bits 15 through 31 in that register. register bit/field types this value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. ro software can read this field. always write the chip reset value. r/w software can read or write this field. r/w1c software can read or write this fiel d. a write of a 0 to a w1c bit does not affect the bit value in the regist er. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. this register type is primarily us ed for clearing interrupt status bits where the read operation provides th e interrupt status and the write of the read value clears only the inte rrupts being reported at the time the register was read. w1c software can write this field. a write of a 0 to a w1c bit does not affect the bit value in the register. a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. a read of the register returns no meaningful data. this register is typically used to clear the corresponding bit in an interrupt register. wo only a write by software is valid; a read of the register returns no meaningful data. register bit/field reset value this value in the register bit diagram shows the bit/field value after any reset, unless noted. 0 bit cleared to 0 on chip reset. 1 bit set to 1 on chip reset. ? nondeterministic. pin/signal notation [ ] pin alternate function; a pin defaults to the signal without the brackets. pin refers to the physical connection on the package. signal refers to the electrical signal encoding of a pin. table 0-1. documentation conventions notation meaning
about this document 20 may 4, 2007 preliminary assert a signal change the value of the sig nal from the logically false state to the logically true state. for active high signals, the asserted signal value is 1 (high); for active low signals, the asserted signal value is 0 (low). the active polarity (high or low) is defined by the signal name (see signal and signal below). deassert a signal change the value of the sig nal from the logically true state to the logically false state. signal signal names are in uppercase and in the courier font. an overbar on a signal name indicates that it is active low. to assert signal is to drive it low; to deassert signal is to drive it high. signal signal names are in uppercase and in the courier font. an active high signal has no overbar. to assert signal is to drive it high; to deassert signal is to drive it low. numbers x an uppercase x indicates any of several values is allowed, where x can be any legal pattern. for example, a binary value of 0x00 can be either 0100 or 0000, a hex value of 0xx is 0x0 or 0x1, and so on. 0x hexadecimal numbers have a prefix of 0x. for example, 0x00ff is the hexadecimal number ff. binary numbers are indicated with a b suffix, for example, 1011b. deci mal numbers are written without a prefix or suffix. table 0-1. documentation conventions notation meaning
lm3s817 data sheet may 4, 2007 21 preliminary 1 architectural overview the luminary micro stellaris? family of micr ocontrollers?the first arm? cortex?-m3 based controllers?brings high-performance 32-bit comput ing to cost-sensitive embedded microcontroller applications. these pioneering parts deliver custom ers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. the lm3s817 controller in the stellaris family of fers the advantages of arm?s widely available development tools, system-on-chip (soc) infras tructure ip applications, and a large user community. additionally, the controller uses arm?s thumb?-compatible thumb-2 instruction set to reduce memory requirements and, thereby, cost. luminary micro offers a complete solution to get to market quickly, with a customer development board, white papers and application notes, and a strong support, sales, and distributor network. 1.1 product features the lm3s817 microcontroller includes the following product features: ? 32-bit risc performance ? 32-bit arm? cortex?-m3 v7m architecture optimized for small-footprint embedded applications ? system timer (systick) provides a simple , 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism ? thumb?-compatible thumb-2-only instruction set processor core for high code density ? 50-mhz operation ? hardware-division and si ngle-cycle-multiplication ? integrated nested vectored in terrupt controller (nvic) providing deterministic interrupt handling ? 26 interrupts with eight priority levels ? memory protection unit (mpu) provides a pr ivileged mode for protected operating system functionality ? unaligned data access, enabling data to be efficiently packed into memory ? atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control ? internal memory ? 64-kb single-cycle flash ? user-managed flash block protection on a 2-kb block basis ? user-managed flash data programming ? user-defined and managed flash-protection block ? 8-kb single-cycle sram ? general-purpose timers ? three timers, each of which can be configured : as a single 32-bit timer, as two 16-bit timers, or to initiate an adc event ? 32-bit timer modes: ? programmable one-shot timer
architectural overview 22 may 4, 2007 preliminary ? programmable periodic timer ? real-time clock when using an external 32.768-khz clock as the input ? user-enabled stalling in pe riodic and one-shot mode when the controller asserts the cpu halt flag during debug ? adc event trigger ? 16-bit timer modes: ? general-purpose timer function with an 8-bit prescaler ? programmable one-shot timer ? programmable periodic timer ? user-enabled stalling when the controller asserts cp u halt flag during debug ? adc event trigger ? 16-bit input capture modes: ? input edge count capture ? input edge time capture ? 16-bit pwm mode: ? simple pwm mode with software-programma ble output inversion of the pwm signal ? arm firm-compliant watchdog timer ? 32-bit down counter with a programmable load register ? separate watchdog clock with an enable ? programmable interrupt generation logic with interrupt masking ? lock register protection from runaway software ? reset generation logic wi th an enable/disable ? user-enabled stalling when the controller asse rts the cpu halt flag during debug ? synchronous serial interface (ssi) ? master or slave operation ? programmable clock bit rate and prescale ? separate transmit and receive fifos, 16 bits wide, 8 locations deep ? programmable interface operation for freescale spi, microwire, or texas instruments synchronous serial interfaces ? programmable data frame size from 4 to 16 bits ? internal loopback test mode for diagnostic/debug testing ? uart ? two fully programmable 16c550-type uarts ? separate 16x8 transmit (tx) and 16x12 re ceive (rx) fifos to reduce cpu interrupt service loading ? programmable baud-rate generator with fractional divider ? programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface
lm3s817 data sheet may 4, 2007 23 preliminary ? fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ? standard asynchronous communication bits for start, stop, and parity ? false-start-bit detection ? line-break generation and detection ? adc ? single- and differential-input configurations ? six 10-bit channels (inputs) when used as single-ended inputs ? sample rate of one million samples/second ? flexible, configurable analog-to-digital conversion ? four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result fifos ? each sequence triggered by software or internal event (timers, analog comparators, pwm or gpio) ? analog comparator ? one independent integrated analog comparator ? configurable for output to: drive an output pin, or generate an interrupt, or initiate an adc sample sequence ? compare external pin input to external pin input or to internal programmable voltage reference ? pwm ? three pwm generator blocks, each with one 16-bit counter, two comparators, a pwm generator, and a dead-band generator ? one 16-bit counter ? runs in down or up/down mode ? output frequency controlled by a 16-bit load value ? load value updates can be synchronized ? produces output signals at zero and load value ? two comparators ? comparator value updates can be synchronized ? produces output signals on match ? pwm generator ? output pwm signal is constructed based on actions taken as a result of the counter and comparator output signals ? produces two independent pwm signals ? dead-band generator ? produces two pwm signals with programmable dead-band delays suitable for driving a half-h bridge ? can be bypassed, leaving input pwm signals unmodified ? flexible output control block with pwm output enable of each pwm signal
architectural overview 24 may 4, 2007 preliminary ? pwm output enable of each pwm signal ? optional output inversion of ea ch pwm signal (polarity control) ? optional fault handling for each pwm signal ? synchronization of timers in the pwm generator blocks ? synchronization of timer/comparator updates across the pwm generator blocks ? interrupt status summary of the pwm generator blocks ? can initiate an adc sample sequence ? gpios ? 1 to 30 gpios, depending on configuration ? 5-v-tolerant input/outputs ? programmable interrupt generation as either edge-triggered or level-sensitive ? bit masking in both read and write operations through address lines ? can initiate an adc sample sequence ? programmable control for gpio pad configuration: ? weak pull-up or pull-down resistors ? 2-ma, 4-ma, and 8-ma pad drive ? slew rate control for the 8-ma drive ? open drain enables ? digital input enables ? power ? on-chip low drop-out (ldo) voltage regulato r, with programmable output user-adjustable from 2.25 v to 2.75 v ? low-power options on controller: sleep and deep-sleep modes ? low-power options for peripherals: software co ntrols shutdown of individual peripherals ? user-enabled ldo unregulated voltage detection and automatic reset ? 3.3-v supply brownout detection a nd reporting via interrupt or reset ? on-chip temperature sensor ? flexible reset sources ? power-on reset (por) ? reset pin assertion ? brown-out (bor) detector alerts to system power drops ? software reset ? watchdog timer reset ? internal low drop-out (ldo) regulator output goes unregulated ? additional features ? six reset sources ? programmable clock source control
lm3s817 data sheet may 4, 2007 25 preliminary ? clock gating to individual peripherals for power savings ? ieee 1149.1-1990 compliant test access port (t ap) controller ? debug access via jtag and serial wire interfaces ? full jtag boundary scan ? industrial-range 48-pin rohs-compliant lqfp package 1.2 target applications ? factory automation and control ? industrial control power devices ? building and home automation ? stepper motors ? brushless dc motors ? ac induction motors
architectural overview 26 may 4, 2007 preliminary 1.3 high-level block diagram figure 1-1. stellaris ? high-level block diagram dcode bus apb bridge sram icode bus arm cortex-m3 flash (including nested vectored interrupt controller (nvic)) memory peripherals lmi jtag test access port (tap) controller system control & clocks universal asynchronous receiver/ transmitters (uarts) synchronous serial interface (ssi) general-purpose timers lm3s817 general-purpose input/outputs (gpios) system peripherals serial communications peripherals pulse width modulator (pwm) motor control peripherals analog-to- digital converter (adc) temperature sensor analog comparators analog peripherals watchdog timer peripheral bus
lm3s817 data sheet may 4, 2007 27 preliminary 1.4 functional overview the following sections provide an overview of th e features of the lm3s817 microcontroller. the chapter number in parenthesis indicates where that feature is discussed in detail. ordering and support information can be found in ?ordering and contact information? on page 379. 1.4.1 arm cortex?-m3 1.4.1.1 processor core (section 2 on page 33) all members of the stellaris product family, including the lm3s817 microcontroller, are designed around an arm cortex?-m3 processor core. the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. section 2, ?arm cortex-m3 processor core,? on page 33 provides an overview of the arm core; the core is detailed in the arm? cortex?-m3 technical reference manual . 1.4.1.2 nested vectored interrupt controller (nvic) the lm3s817 controller includes the arm nested vectored interrupt controller (nvic) on the arm cortex-m3 core. the nvic and cortex-m3 prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables efficient interrupt entry. the processor supports tail-chaining, which enab les back-to-back interrupts to be performed without the overhead of state saving and restorati on. software can set eight priority levels on 7 exceptions (system handlers) and 26 interrupts. section 4, ?interrupts,? on page 43 provides an ov erview of the nvic cont roller and the interrupt map. exceptions and interrupts are detailed in the arm? cortex?-m3 technical reference manual . 1.4.2 motor control peripherals to enhance motor control, the lm3s817 contro ller features pulse width modulation (pwm) outputs. 1.4.2.1 pwm pulse width modulation (pwm) is a powerful techni que for digitally encoding analog signal levels. high-resolution counters are used to generate a sq uare wave, and the duty cycle of the square wave is modulated to encode an analog signal . typical applications include switching power supplies and motor control. on the lm3s817, pwm motion control functionalit y can be achieved through dedicated, flexible motion control hardware (the pwm pins) or through the motion control features of the general-purpose timers (using the ccp pins). pwm pins (section 15 on page 320) the lm3s817 pwm module consists of three pwm generator blocks and a control block. each pwm generator block contains one timer (16-bit down or up/down counter), two comparators, a pwm signal generator, a dead-band generator, and an interrupt/adc-trigger selector. the control block determines the polarity of the pwm signals, and which signals are passed through to the pins.
architectural overview 28 may 4, 2007 preliminary each pwm generator block produces two pwm signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. ccp pins (?16-bit pwm mode? on page 162) the general-purpose timer module?s ccp (capture compare pwm) pins are software programmable to support a simple pwm mode with a software-programmable output inversion of the pwm signal. 1.4.3 analog peripherals to handle analog signals, the lm3s817 controller offers an analog-to-digital converter (adc) and an analog comparator. 1.4.3.1 adc (section 11 on page 208) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number. the stellaris adc module features 10-bit conversi on resolution and supports six input channels, plus an internal temperature sensor. four buffered sample sequences allow rapid sampling of up to six analog input sources without controller interv ention. each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 1.4.3.2 analog comparator (section 14 on page 309) an analog comparator is a perip heral that compares two analog voltages, and provides a logical output that signals the comparison result. the lm3s817 controller provides one independent integrated analog comparator that can be configured to drive an output or generate an interrupt or adc event. a comparator can compare a test voltage against any one of these voltages: ? an individual external reference voltage ? a single external reference voltage ? a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to sig nal the application via interrupts or triggers to the adc to cause it to start capturing a sample sequ ence. the interrupt generation and adc triggering logic is separate. this means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. 1.4.4 serial communications peripherals the lm3s817 controller supports both asynchro nous and synchronous serial communications with two fully programmable 16c550-type uarts and ssi serial communications. 1.4.4.1 uart (section 12 on page 238) a universal asynchronous receiver /transmitter (uart) is an integrated circuit used for rs-232c serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. the lm3s817 controller includes two fully programmable 16c550-type uarts that support data transfer speeds up to 460.8 kbps. (although simila r in functionality to a 16c550 uart, it is not register compatible.)
lm3s817 data sheet may 4, 2007 29 preliminary separate 16x8 transmit (tx) and 16x12 receive (r x) fifos reduce cpu inte rrupt service loading. the uart can generate individually masked inte rrupts from the rx, tx, modem status, and error conditions. the module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 ssi (section 13 on page 274) synchronous serial interface (s si) is a four-wire bi-directio nal communications interface. the stellaris ssi module provides the function ality for synchronous serial communications with peripheral devices, and can be configured to use the freescale spi, microwire, or ti synchronous serial interface frame formats. the si ze of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. the ssi module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. the tx and rx paths are buffered with internal fifos, allowing up to eight 16-bit values to be stored independently. the ssi module can be configured as either a master or slave device. as a slave device, the ssi module can also be configured to disable its outpu t, which allows a master device to be coupled with multiple slave devices. the ssi module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the ssi module?s input clock. bit rates are generated based on the input clock and the maximum bit rate is determined by the c onnected peripheral. 1.4.5 system peripherals 1.4.5.1 programmable gpios (section 8 on page 115) general-purpose input/ output (gpio) pins of fer flexibility for a variety of connections. the stellaris gpio module is composed of five physical gpio blocks, each corresponding to an individual gpio port. the gpio module is firm-c ompliant (compliant to the arm foundation ip for real-time microcontrollers sp ecification) and supports 1 to 30 programmable input/output pins. the number of gpios available depends on t he peripherals being used (see table 17-4 on page 358 for the signals available to each gpio pin). the gpio module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for gpio pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 three programmable timers (section 9 on page 153) programmable timers can be used to count or time external events that drive the timer input pins. the stellaris general-purpose timer module (gptm) contains three gptm blocks. each gptm block provides two 16-bit timer/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-time clock (rtc). timers can also be used to tri gger analog-to-digital (adc) conversions. when configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or real-time clock (rtc). when in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. a 16-bit timer can also be configured for event capture or pulse width modulation (pwm) generation. 1.4.5.3 watchdog timer (section 10 on page 185) a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain co ntrol when a system has failed due to a software error or to the failure of an external device to respond in the expected way.
architectural overview 30 may 4, 2007 preliminary the stellaris watchdog timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be writte n to prevent the timer configuration from being inadvertently altered. 1.4.6 memory peripherals the stellaris controllers offer both sram and flash memory. 1.4.6.1 sram (section 7.2.1 on page 98) the lm3s817 static random access memory (sram) controller supports 8 kb sram. the internal sram of the stellaris devices is loca ted at address 0x2000.0000 of the device memory map. to reduce the number of time consumin g read-modify-write (rmw) operations, arm has introduced bit-banding technology in the new cortex-m3 processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 flash (section 7.2.2 on page 99) the lm3s817 flash controller supports 64 kb of fl ash memory. the flash is organized as a set of 1-kb blocks that can be individually erased. eras ing a block causes the entire contents of the block to be reset to all 1s. these blocks are paired into a set of 2- kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programm ed, protecting the contents of those blocks from being modified. execute-only bl ocks cannot be erased or programmed, and can only be read by the controller in struction fetch mechanism, protecti ng the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 additional features 1.4.7.1 memory map (section 3 on page 41) a memory map lists the location of instructions and data in memory. the memory map for the lm3s817 controller can be found on page 41. register addresses are given as a hexadecimal increment, relative to the module?s base address as shown in the memory map. the arm? cortex?-m3 technical reference manual provides further information on the memory map. 1.4.7.2 jtag tap controller (section 5 on page 46) the joint test action group (jtag) port provides a standardized se rial interface for controlling the test access port (tap) and associated test logic. the tap, jtag instruction register, and jtag data registers can be used to test the intercon nects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal o peration. the jtag port provides a high deg ree of testability and chip-level access at a low cost. the jtag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially in to the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of t he tap controller. for detailed information on the operation of the jtag port and tap controller, please refer to the ieee standard 1149.1-test access port and boundary-scan architecture .
lm3s817 data sheet may 4, 2007 31 preliminary the lmi jtag controller works with the arm jtag c ontroller built into the co rtex-m3 core. this is implemented by multiplexing the tdo outputs from both jtag contro llers. arm jtag instructions select the arm tdo output while lmi jtag in structions select the lmi tdo outputs. the multiplexer is controlled by the lmi jtag cont roller, which has comprehensive programming for the arm, lmi, and unimplemented jtag instructions. 1.4.7.3 system control and clocks (section 6 on page 56) system control determines the overall operation of the device. it provides information about the device, controls the clocking of the device and in dividual peripherals, and handles reset detection and reporting. 1.4.8 hardware details details on the pins and package can be found in the following sections: ? section 16, ?pin diagram,? on page 349 ? section 17, ?signal tables,? on page 350 ? section 18, ?operating characteristics,? on page 360 ? section 19, ?electrical characteristics,? on page 361 ? section 20, ?package information,? on page 373
architectural overview 32 may 4, 2007 preliminary 1.5 system block diagram figure 1-2. lm3s817 controller system-level block diagram flash sram apb bridge icode dcode gnd vdd_3.3v ldo vdd_2.5v ldo system control & clocks osc0 osc1 rst pll watchdog timer por bor iosc debug arm cortex-m3 nvic cm3core bus uart0 pa1/u0tx pa0/u0rx gpio port a ssi pa3/ssifss pa2/ssiclk pa5/ssitx pa4/ssirx (8 kb) (64 kb) (50 mhz) gpio port b gpio port c pc1/tms/swdio pc0/tck/swclk pc3/tdo/swo pc2/tdi pb3/fault pb2 pb5/c0o pb4/c0- pb6/c0+ gp timer2 gp timer0 pb7/trst analog comparator gp timer1 gpio port d adc temperature sensor gpio port e adc4 adc5 adc2 adc0 adc1 pe0/pwm4 pe1/pwm5 pwm0 pd0/pwm0 pd1/pwm1 pd4/ccp0 pd5/ccp2 pd2/u1rx pd3/u1tx pwm1 pb1/pwm3 pb0/pwm2 adc3 pc6/ccp3 pc7/ccp4 pc5/ccp1 pc4/ccp5 lm3s817 jtag swd/swo pwm2 peripheral bus uart1
lm3s817 data sheet may 4, 2007 33 preliminary 2 arm cortex-m3 processor core the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implemen tation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. features include: ? compact core. ? thumb-2 instruction set, delivering the high-pe rformance expected of an arm core in the memory size usually associated with 8- and 16 -bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ? exceptional interrupt handling, by implementing the register manipulations required for handling an interr upt in hardware. ? memory protection unit (mpu) to provide a privileged mode of operation for complex applications. ? full-featured debug solution with a: ? serial wire jtag debug port (swj-dp) ? flash patch and breakpoint (fpb) unit for implementing breakpoints ? data watchpoint and trigger (dwt) unit for implementing watchpoints, trigger resources, and system profiling ? instrumentation trace macrocell (itm) for support of printf style debugging ? trace port interface unit (tpiu) for bridging to a trace port analyzer the stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive em bedded microcontroller applicatio ns, such as factory automation and control, industrial control power devices, and building and home automation. for more information on the arm cortex-m3 processor core, see the arm? cortex?-m3 technical reference manual . for information on swj-dp, see the coresight? design kit technical reference manual .
arm cortex-m3 processor core 34 may 4, 2007 preliminary 2.1 block diagram figure 2-1. cpu block diagram 2.2 functional description important: the arm? cortex?-m3 technical reference manual describes all the features of an arm cortex-m3 in detail. however, these features differ based on the implementation. this section describes the stellaris implementation. luminary micro has implemented the arm cortex-m 3 core as shown in figure 2-1. as noted in the arm? cortex?-m3 technical reference manual , several cortex-m3 components are flexible in their implementation: sw/jtag-dp, etm, tpiu, the rom table, the mpu, and the nested vectored interrupt controller (nvic). each of th ese is addressed in the sections that follow. 2.2.1 serial wire and jtag debug luminary micro has replaced the arm sw-dp and jtag-dp with the arm coresight?-compliant serial wire jtag debug po rt (swj-dp) interface. this means chapter 12, ?debug port,? of the arm? cortex?-m3 technical reference manual does not apply to stellaris devices. the swj-dp interface combines the swd and jtag debug ports into one module. see the coresight? design kit technical reference manual for details on swj-dp. private peripheral bus (internal ) data watchpoint and trace interrupts debug sleep instrumentation trace macrocell trace port interface unit cm3 core instructions data flash patch and breakpoint memory protection unit adv. high- perf. bus access port nested vectored interrupt controller serial wire jtag debug port bus matrix adv. peripheral bus i-code bus d-code bus system bus rom table private peripheral bus (external) serial wire output trace port (swo) arm cortex-m3
lm3s817 data sheet may 4, 2007 35 preliminary 2.2.2 embedded trace macrocell (etm) etm was not implemented in the stellaris devices. this means chapters 15 and 16 of the arm? cortex?-m3 technical reference manual can be ignored. 2.2.3 trace port interface unit (tpiu) the tpiu acts as a bridge between the cortex-m3 trace data from the itm, and an off-chip trace port analyzer. the stellaris devices have implem ented tpiu as shown in figure 2-2. this is similar to the non-etm version described in the arm? cortex?-m3 technical reference manual , however, swj-dp only provides swv output for the tpiu. figure 2-2. tpiu block diagram 2.2.4 rom table the default rom table was implemented as described in the arm? cortex?-m3 technical reference manual . 2.2.5 memory protection unit (mpu) the memory protection unit (mpu) is includ ed on the lm3s817 controller and supports the standard armv7 protected memory system archit ecture (pmsa) model. the mpu provides full support for protection regions, overlapping protec tion regions, access permissions, and exporting memory attributes to the system. 2.2.6 nested vectored inte rrupt controller (nvic) the nested vectored inte rrupt controller (nvic): ? facilitates low-latency exception and interrupt handling ? controls power management ? implements system control registers the nvic supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. the nvic and the processor core interfac e are closely coupled, which enables low latency atb interface asynchronous fifo apb interface trace out (serializer) debug atb slave port apb slave port serial wire trace port (swo)
arm cortex-m3 processor core 36 may 4, 2007 preliminary interrupt processing and efficient processing of late arriving interrup ts. the nvic maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. you can only fully access the nvic from privileged mode, but you can pend interrupts in user-mode if you enable the configuration control register (see the arm? cortex?-m3 technical reference manual ). any other user-mode ac cess causes a bus fault. all nvic registers are accessible using byte , halfword, and word unless otherwise stated. all nvic registers and system debug registers are little endian rega rdless of the endianness state of the processor. 2.2.6.1 interrupts the arm? cortex?-m3 technical reference manual describes the maximum number of interrupts and interrupt priorities. the lm3s817 microcontroller supports 26 interrupts with eight priority levels. 2.2.6.2 system timer (systick) cortex-m3 includes an in tegrated system timer, systick. systick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero count er with a flexible control mechanism. the counter can be used in several different ways, for example: ? an rtos tick timer which fires at a programmable rate (for example, 100 hz) and invokes a systick routine. ? a high-speed alarm timer using the system clock. ? a variable rate alarm or signal timer?the duration is range-dependent on the reference clock used and the dynamic range of the counter. ? a simple counter. software can use this to measure time to completion and time used. ? an internal clock source control based on missing/meeting durations. the countflag bit-field in the control and status register c an be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. functional description the timer consists of three registers: ? a control and status counter to configure its clock, enable the counter, enable the systick interrupt, and determine counter status. ? the reload value for the counter, used to provide the counter's wrap value. ? the current value of the counter. a fourth register, the systick calibration value register, is not implemented in the stellaris devices. when enabled, the timer counts down from the rel oad value to zero, reload s (wraps) to the value in the systick reload value register on the next clock edge, then decrements on subsequent clocks. writing a value of zero to the reload value register disabl es the counter on the next wrap. when the counter reaches zero, the countflag st atus bit is set. the countflag bit clears on reads. writing to the current value register clears the register and the countflag status bit. the write does not trigger the systick exception logic. on a read, the current value is the value of the register at the time the register is accessed.
lm3s817 data sheet may 4, 2007 37 preliminary if the core is in debug state (halted), the coun ter will not decrement. the timer is clocked with respect to a reference clock. the reference cl ock can be the core clock or an external clock source.
arm cortex-m3 processor core 38 may 4, 2007 preliminary register 1: systick control and status register use the systick control and status regi ster to enable the systick features. bit/field name type reset description 31:17 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 16 countflag r/w 0 returns 1 if timer counted to 0 since last time this was read. clears on read by application. if read by the debugger using the dap, this bit is cleared on read-only if the mastertype bit in the ahb-ap control register is set to 0. otherwise, the countflag bit is not changed by the debugger read. 15:3 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 2 clksource r/w 0 0 = external reference clock. (not implemented for stellaris microcontrollers.) 1 = core clock. if no reference clock is provided, it is held at 1 and so gives the same time as the core clock. the core clock must be at least 2.5 times faster than the reference clock. if it is not, the count values are unpredictable. 1 tickint r/w 0 1 = counting down to 0 pends the systick handler. 0 = counting down to 0 does not pend the systick handler. software can use the countflag to determine if ever counted to 0. 0 enable r/w 0 1 = counter operates in a mu lti-shot way. that is, counter loads with the reload value and then begins counting down. on reaching 0, it sets the countfl ag to 1 and optionally pends the systick handler, based on tickint. it then loads the reload value again, and begins counting. 0 = counter disabled. ro 0 systick control and status address: 0xe000e010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w reserved tickint enable countflag clksource reserved
lm3s817 data sheet may 4, 2007 39 preliminary register 2: systick reload value register use the systick reload value register to specify the start value to load into the current value register when the counter reaches 0. it can be any value between 1 and 0x00ffffff. a start value of 0 is possible, but has no effect because the systick interrupt and countflag are activated when counting from 1 to 0. therefore, as a multi-shot timer, repeated over an d over, it fires every n+1 clock pulse, where n is any value from 1 to 0x00ffffff. so, if the tick interrupt is required every 100 clock pulses, 99 must be written into the reload. if a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be writ ten. for example, if a ti ck is next required after 400 clock pulses, 400 must be written into the reload. bit/field name type reset description 31:24 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 23:0 reload w1c - value to load into the systick current value register when the counter reaches 0. ro 0 systick reload value address: 0xe000e014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 0000000- ------- ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w - reset type --------------- r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved reload reload
arm cortex-m3 processor core 40 may 4, 2007 preliminary register 3: systick current value register use the systick current value register to find the current value in the register. 2.2.6.3 systick calibration value register the systick calibration value register is not implemented. systick current value register bit assignments bit/field name type reset description 31:24 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 23:0 current w1c - current value at the time the register is accessed. no read-modify-write protection is provided, so change with care. this register is write-clear. writing to it with any value clears the register to 0. clearing this regi ster also clears the countflag bit of the systick control and status register. ro 0 systick current value address: 0xe000e018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 0000000- ------- ro ro ro ro ro ro ro w1c w1c w1c w1c w1c w1c w1c w1c w1c - reset type --------------- w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reserved current current
lm3s817 data sheet may 4, 2007 41 preliminary 3 memory map the memory map for the lm3s817 is provided in table 3-1. in this manual, register addresses are given as a hexadecimal increment, relative to the module?s base address as shown in the memory map. see also chapter 4, ?memory map? in the arm? cortex?-m3 technical reference manual . table 3-1. memory map (sheet 1 of 2) start end description for details on registers, see ... memory 0x00000000 0x00007fff on-chip flash page 103 0x00008000 0x1fffffff reserved a 0x20000000 0x20001fff bit-banded on-chip sram - 0x20002000 0x200fffff reserved a - 0x22000000 0x2203ffff bit-band alias of 0x20000000 through 0x20001fff - 0x22040000 0x23ffffff reserved a - firm peripherals 0x40000000 0x40000fff watchdog timer page 187 0x40001000 0x40003fff reserved for three additional watchdog timers (per firm specification) a - 0x40004000 0x40004fff gpio port a page 122 0x40005000 0x40005fff gpio port b page 122 0x40006000 0x40006fff gpio port c page 122 0x40007000 0x40007fff gpio port d 0x40008000 0x40008fff ssi page 285 0x40009000 0x4000bfff reserved for three additional ssis (per firm specification) a - 0x4000c000 0x4000cfff uart0 page 244 0x4000d000 0x4000dfff uart1 page 244 0x4000e000 0x4000ffff reserved for two additional uarts (per firm specification) a - 0x40010000 0x4001ffff reserved for future firm peripherals a - peripherals 0x40020000 0x40023fff reserved a - 0x40025000 0x40027fff reserved a - 0x40028000 0x40028fff pwm page 325
memory map 42 may 4, 2007 preliminary 0x40029000 0x4002bfff reserved a - 0x4002c000 0x4002ffff reserved a - 0x40030000 0x40030fff timer0 page 164 0x40031000 0x40031fff timer1 page 164 0x40032000 0x40032fff timer2 page 164 0x40033000 0x40037fff reserved a - 0x40038000 0x40038fff adc page 213 0x40039000 0x4003bfff reserved a - 0x4003c000 0x4003cfff analog comparator page 312 0x4003d000 0x400fcfff reserved a - 0x400fd000 0x400fdfff flash control page 103 0x400fe000 0x400fffff system control page 63 0x40100000 0x41ffffff reserved a - 0x42000000 0x43ffffff bit-band alias of 0x40000000 through 0x400fffff - 0x44000000 0xdfffffff reserved a - private peripheral bus 0xe0000000 0xe0000fff instrumentation trace macrocell (itm) arm? cortex?-m3 technical reference manual 0xe0001000 0xe0001fff data watchpoint and trace (dwt) 0xe0002000 0xe0002fff flash patch and breakpoint (fpb) 0xe0003000 0xe000dfff reserved a 0xe000e000 0xe000efff nested vectored interrupt controller (nvic) 0xe000f000 0xe003ffff reserved a 0xe0040000 0xe0040fff trace po rt interface unit (tpiu) 0xe0041000 0xe0041fff reserved a - 0xe0042000 0xe00fffff reserved a - 0xe0100000 0xffffffff reserved for vendor peripherals a - a. all reserved space returns a bus fault when read or written. table 3-1. memory map (sheet 2 of 2) start end description for details on registers, see ...
lm3s817 data sheet may 4, 2007 43 preliminary 4interrupts the arm cortex-m3 processor and t he nested vectored interrupt controller (nvic) prioritize and handle all exceptions. all exceptions are hand led in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the ve ctor is fetched in parallel to the state saving, which enables efficient interrupt entry. the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. table 4-1 lists all the exceptions. software can set eight priority levels on seven of these exceptions (system handlers) as we ll as on 26 interrupts (listed in table 4-2). priorities on the system handlers are set wi th the nvic system handler priority registers. interrupts are enabled through the nvic interrupt set enable register and prioritized with the nv ic interrupt priority registers. you can also group priori ties by splitting priority levels into pre-emption priorities and subpriorities. all the interrupt registers are desc ribed in chapter 8, ?nes ted vectored interrupt controller? in the arm? cortex?-m3 technical reference manual . internally, the highest user-settable priority (0) is treated as fourth priority , after a reset, nmi, and a hard fault. note that 0 is the default priority for all the settable priorities. if you assign the same priority leve l to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. for example, if both gpio port a and gpio port b are priority level 1, then gpio port a has higher priority. see chapter 5, ?exceptions? and chapter 8, ?nested vectored interrupt controller? in the arm? cortex?-m3 technical reference manual for more information on exceptions and interrupts. table 4-1. exception types exception type position priority a description - 0 - stack top is loaded from first entry of vector table on reset. reset 1 - 3 (highest) invoked on power up and warm reset. on first instruction, drops to lowest priority (and then is called the base level of activation). this is asynchronous. non - maskable interrupt (nmi) 2 - 2 cannot be stopped or preempted by any exception but reset. this is asynchronous. an nmi is only producible by software, using the nvic interrupt control state register. hard fault 3 - 1 all classes of fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. this is synchronous. memory management 4 settable mpu mismatch, incl uding access violation and no match. this is synchronous. the priority of this exception can be changed. bus fault 5 settable pre - fetch fault, memory access fault, and other address/memory related faults. this is synchronous when precise and asynchronous when imprecise. you can enable or disable this fault.
interrupts 44 may 4, 2007 preliminary usage fault 6 settable usage fault, such as undefined instruction executed or illegal state transition attempt. this is synchronous. - 7 - 10 - reserved. svcall 11 settable system service call with svc instruction. this is synchronous. debug monitor 12 settable debug monitor (when not halting). this is synchronous, but only active when enabled. it does not activate if lower pr iority than the current activation. - 13 - reserved. pendsv 14 settable pendable request for system service. this is asynchronous and only pended by software. systick 15 settable system tick timer ha s fired. this is asynchronous. interrupts 16 and above settable asserted from outside the arm cortex - m3 core and fed through the nvic (prioritized). these are all asynchronous. table 4-2 lists the interrupts on the lm3s817 controller. a. 0 is the default priority for all the settable priorities. table 4-2. interrupts interrupt (bit in interrupt registers) description 0 gpio port a 1 gpio port b 2 gpio port c 3 gpio port d 4 gpio port e 5uart0 6uart1 7 ssi 8 reserved 9pwm fault 10 pwm generator 0 11 pwm generator 1 12 pwm generator 2 table 4-1. exception types (continued) exception type position priority a description
lm3s817 data sheet may 4, 2007 45 preliminary 13 reserved 14 adc sequence 0 15 adc sequence 1 16 adc sequence 2 17 adc sequence 3 18 watchdog timer 19 timer0a 20 timer0b 21 timer1a 22 timer1b 23 timer2a 24 timer2b 25 analog comparator 0 26-27 reserved 28 system control 29 flash control 30-31 reserved table 4-2. interrupts (continued) interrupt (bit in interrupt registers) description
jtag interface 46 may 4, 2007 preliminary 5 jtag interface the joint test action group (jtag) port is an ieee standard that defines a test access port and boundary scan architecture for digital integrat ed circuits and provides a standardized serial interface for controlling the associ ated test logic. the tap, inst ruction register (ir), and data registers (dr) can be used to test the interconn ections of assembled printed circuit boards and obtain manufacturing information on the component s. the jtag port also provides a means of accessing and controlling design-for-t est features such as i/o pin observation and control, scan testing, and debugging. the jtag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially in to the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of t he tap controller. for detailed information on the operation of the jtag port and tap controller, please refer to the ieee standard 1149.1-test access port and boundary-scan architecture . the lmi jtag controller works with the arm jtag c ontroller built into the co rtex-m3 core. this is implemented by multiplexing the tdo outputs from both jtag contro llers. arm jtag instructions select the arm tdo output while lmi jtag in structions select the lmi tdo outputs. the multiplexer is controlled by the lmi jtag cont roller, which has comprehensive programming for the arm, lmi, and unimplemented jtag instructions. the jtag module has the following features: ? ieee 1149.1-1990 compat ible test access port (tap) controller ? four-bit instructio n register (ir) chain for storing jtag instructions ? ieee standard in structions: ? bypass instruction ? idcode instruction ? sample/preload instruction ? extest instruction ? intest instruction ? arm additional instructions: ? apacc instruction ? dpacc instruction ? abort instruction ? integrated arm serial wire debug (swd) see the arm? cortex?-m3 technical reference manual for more information on the arm jtag controller.
lm3s817 data sheet may 4, 2007 47 preliminary 5.1 block diagram figure 5-1. jtag module block diagram 5.2 functional description a high-level conceptual drawing of the jtag modu le is shown in figure 5-1. the jtag module is composed of the test access port (tap) controlle r and serial shift chains with parallel update registers. the tap controller is a si mple state machine controlled by the trst , tck and tms inputs. the current state of the tap controller depends on the current value of trst and the sequence of values captured on tms at the rising edge of tck . the tap controller determines when the serial shift chains capture new data, shift data from tdi towards tdo , and update the parallel load registers. the current state of th e tap controller also determines whether the instruction register (ir) chain or one of the data register (dr) chai ns is being accessed. the serial shift chains with paralle l load registers are comprised of a single instruction register (ir) chain and multiple data register (dr) chains. the current instruction loaded in the parallel load register determines which dr chain is captur ed, shifted, or updated during the sequencing of the tap controller. some instructions, like extest and intest, operate on data currently in a dr chain and do not capture, shift, or update any of the chains. instructions that are not implemented decode to the bypass instruction to ensure th at the serial path between tdi and tdo is always connected (see table 5-2 on page 52 for a list of implemented instructions). see ?jtag and boundary scan? on page 368 for jtag timing diagrams. instruction register (ir) tap controller bypass data register boundary scan data register idcode data register abort data register dpacc data register apacc data register trst tck tms tdi tdo cortex-m3 debug port
jtag interface 48 may 4, 2007 preliminary 5.2.1 jtag interface pins the jtag interface consists of five standard pins: trst , tck , tms , tdi , and tdo . these pins and their associated reset state are given in table 5-1. detailed information on each pin follows. 5.2.1.1 test reset input (trst ) the trst pin is an asynchronous active low input sign al for initializing and resetting the jtag tap controller and associated jtag circuitry. when trst is asserted, the tap controller resets to the test-logic-reset state and remains there while trst is asserted. when the tap controller enters the test-logic-reset state, the jtag in struction register (ir) resets to the default instruction, idcode. by default, the internal pull-up resistor on the trst pin is enabled after reset. changes to the pull-up resistor settings on gpio port b should ensure that the internal pull-up resistor remains enabled on pb7 / trst ; otherwise jtag communication could be lost. 5.2.1.2 test clock input (tck) the tck pin is the clock for the jtag module. this cl ock is provided so the test logic can operate independently of any other system clocks. in a ddition, it ensures that multiple jtag tap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50% duty cycle. when necessary, tck can be stopped at 0 or 1 for extended periods of time. while tck is stopped at 0 or 1, the state of the tap controller does not change and data in the jtag instruction and data registers is not lost. by default, the internal pull-up resistor on the tck pin is enabled after reset. this assures that no clocking occurs if the pin is not driven from an ex ternal source. the internal pull-up and pull-down resistors can be turned off to save internal power as long as the tck pin is constantly being driven by an external source. 5.2.1.3 test mode select (tms) the tms pin selects the next state of the jtag tap controller. tms is sampled on the rising edge of tck . depending on the current tap state and the sampled value of tms , the next state is entered. because the tms pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tms to change on the falling edge of tck . holding tms high for five consecutive tck cycles drives the tap controller state machine to the test-logic-reset state. when the tap controller enters the test-logic-reset state, the jtag instruction register (ir) resets to the default instruction, idcode. therefore, this sequence can be used as a reset mechanism, similar to asserting trst . the jtag test access port state machine can be seen in its entirety in figure 5-2 on page 50. table 5-1. jtag port pins reset state pin name data direction internal pull-up internal pull-down drive strength drive value trst input enabled disabled n/a n/a tck input enabled disabled n/a n/a tms input enabled disabled n/a n/a tdi input enabled disabled n/a n/a tdo output enabled disabled 2-ma driver high-z
lm3s817 data sheet may 4, 2007 49 preliminary by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms ; otherwise jtag communication could be lost. 5.2.1.4 test data input (tdi) the tdi pin provides a stream of serial inform ation to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current tap state and the current instruction, presents this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck , the ieee standard 1149.1 expects the value on tdi to change on the falling edge of tck . by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi ; otherwise jtag communication could be lost. 5.2.1.5 test data output (tdo) the tdo pin provides an output stream of serial in formation from the ir chain or the dr chains. the value of tdo depends on the current tap state, the current instruction, and the data in the chain being accessed. in order to save power when the jtag port is not being used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1149.1 expects the value on tdo to change on the falling edge of tck . by default, the internal pull-up resistor on the tdo pin is enabled after reset. this assures that the pin remains at a constant logic level when the jt ag port is not being used. the internal pull-up and pull-down resistors can be turned off to save internal power if a high-z output value is acceptable during certain tap controller states. 5.2.2 jtag tap controller the jtag tap controller state machine is shown in figure 5-2 on page 50. the tap controller state machine is reset to the test-logic-reset state on the assertion of a power-on-reset (por) or the assertion of trst . asserting the correct sequence on the tms pin allows the jtag module to shift in new instructions, shift in data, or id le during extended testing sequences. for detailed information on the function of the tap controller and the operations that occur in each state, please refer to ieee standard 1149.1 .
jtag interface 50 may 4, 2007 preliminary figure 5-2. test access port state machine 5.2.3 shift registers the shift registers consist of a serial shift regist er chain and a parallel load register. the serial shift register chain samples spec ific information during the tap controller?s capture states and allows this information to be shifted out of tdo during the tap controller?s shift states. while the sampled data is being shifted out of the chain on tdo , new data is being shifted into the serial shift register on tdi . this new data is stored in the parallel load register during the tap controller?s update states. each of the shift registers is discu ssed in detail in ?shift registers? on page 50. 5.2.4 operational considerations there are certain operational considerations when using the jtag module. because the jtag pins can be programmed to be gpios, board conf iguration and reset conditions on these pins must be considered. in addition, because the jtag module has integrated arm serial wire debug, the method for switching between these two operational modes requires clarification. 5.2.4.1 gpio functionality when the controller is reset with either a por or rst , the jtag port pins default to their jtag configurations. the default configuration includes enabling the pull-up resistors (setting gpiopur test logic run test idle select dr scan select ir scan capture dr capture ir shift dr shift ir exit 1 dr exit 1 ir exit 2 dr exit 2 ir pause dr pause ir update dr update ir 11 1 11 1 11 11 11 11 11 00 0 0 0 0 00 00 00 0 0 0 0
lm3s817 data sheet may 4, 2007 51 preliminary to 1 for pb7 and pc[3:0] ) and enabling the alternate hardware function (setting gpioafsel to 1 for pb7 and pc[3:0] ) on the jtag pins. it is possible for software to configure these pins as gpios after reset by writing 0s to pb7 and pc[3:0] in the gpioafsel register. if the user does not require the jtag port for debugging or board-level testing, this provides fi ve more gpios for use in the design. caution ? if the jtag pins ar e used as gpios in a design, pb7 and pc2 cannot have external pull-down resistors connected to both of them at the same time. if both pins are pulled low during reset, the controller has unpredictable behavior. if this happens, remove one or both of the pull-down resistors, and apply rst or power-cycle the part in addition, it is possible to create a software sequence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into flash immediately changes the jtag pins to their gpio functionality, the debugger does not have enough time to connect and halt the controller before the jtag pin functiona lity switches. this locks the debugger out of the part. this can be avoided with a software routin e that restores jtag functionality using an external trigger. 5.2.4.2 arm serial wire debug (swd) in order to seamlessly integrate the arm serial wire debug (swd) functionality, a serial-wire debugger must be able to connect to the cortex-m3 core without having to perform, or have any knowledge of, jtag cycles. this is accomplished wi th a swd preamble that is issued before the swd session begins. the preamble used to enable the swd interface of the swj-dp module starts with the tap controller in the test-logic-reset state. from here, the preamble sequences the tap controller through the following states: run test idle, select dr, select ir, capture ir, exit1 ir, update ir, run test idle, select dr, select ir, capture ir, exit1 ir, update ir, run test idle, select dr, select ir, and test-logic-reset states. stepping through the jtag tap instruction register (ir) load sequences of the tap state machine twice without shifting in a new instruct ion enables the swd interface and disables the jtag interface. for more information on th is operation and the swd interface, see the arm? cortex?-m3 technical reference manual and the arm? coresight technical reference manual . because this sequence is a valid series of jtag operations that could be issued, the arm jtag tap controller is not fully compliant to the ieee standard 1149.1 . this is the only instance where the arm jtag tap controller does not meet full comp liance with the specific ation. due to the low probability of this sequence occu rring during normal oper ation of the tap controller, it should not affect normal performance of the jtag interface. 5.3 initialization and configuration after a power-on-reset or an external reset ( rst ), the jtag pins are automatically configured for jtag communication. no user-def ined initialization or configuration is need ed. however, if the user application changes these pins to their gpio function, they must be configured back to their jtag functionality before jtag communication can be restored. this is done by enabling the five jtag pins ( pb7 and pc[3:0] ) for their alternate function using the gpioafsel register.
jtag interface 52 may 4, 2007 preliminary 5.4 register descriptions there are no apb-accessible registers in the jtag tap contro ller or shift regi ster chains. the registers within the jtag controller are all acce ssed serially through the tap controller. the registers can be broken down into two main cate gories: instruction regist ers and data registers. 5.4.1 instruction register (ir) the jtag tap instruction register (ir) is a four-bit serial scan chain with a parallel load register connected between the jtag tdi and tdo pins. when the tap controller is placed in the correct states, bits can be shifted into the instruction re gister. once these bits have been shifted into the chain and updated, they are interpreted as the curr ent instruction. the decode of the instruction register bits is shown in table 5-2. a detailed explanation of each instruction, along with its associated data register, follows. 5.4.1.1 extest instruction the extest instruction does not have an a ssociated data register chain. the extest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instructio n. when the extest instruction is present in the instruction register, the preloaded data in the boundary scan data register associated with the outputs and output enables are used to drive the gpio pads rather than the signals coming from the core. this allows tests to be developed that drive known val ues out of the controller, which can be used to verify connectivity. 5.4.1.2 intest instruction the intest instruction does not have an associat ed data register chain. the intest instruction uses the data that has been preloaded into the boundary scan data register using the sample/ preload instruction. when the in test instruction is present in the instruction register, the preloaded data in the boundary scan data regist er associated with the inputs are used to drive the signals going into the core rather than the signals coming from the gpio pads. this allows table 5-2. jtag instruction register commands ir[3:0] instruction description 0000 extest drives the values preloaded into the boundary scan chain by the sample/preload instruction onto the pads. 0001 intest drives the values preloaded into the boundary scan chain by the sample/preload instructio n into the controller. 0010 sample / preload captures the current i/o values and shifts the sampled values out of the boundary scan chain while new preload data is shifted in. 1000 abort shifts data into the arm debug port abort register. 1010 dpacc shifts data into and out of the arm dp access register. 1011 apacc shifts data into and out of the arm ac access register. 1110 idcode loads manufacturing information defined by the ieee standard 1149.1 into the idcode chain and shifts it out. 1111 bypass connects tdi to tdo through a single shift register chain. all others reserved defaults to t he bypass instruction to ensure that tdi is always connected to tdo .
lm3s817 data sheet may 4, 2007 53 preliminary tests to be developed that drive known values into the controller, which can be used for testing. it is important to note that although the rst input pin is on the boundary scan data register chain, it is only observable. 5.4.1.3 sample/prel oad instruction the sample/preload inst ruction connects the boundary scan data register chain between tdi and tdo . this instruction samples the current state of the pad pins for observation and preloads new test data. each gpio pad has an associated input, output, and output enable signal. when the tap controller enters the capture dr stat e during this instruction, the input, output, and output-enable signals to each of the gpio pads are captured. these samples are serially shifted out of tdo while the tap controller is in the shift dr state and can be used for observation or comparison in various tests. while these samples of the inputs, outputs, and output enables are being shifted out of the boundary scan data register, new data is being shifted into the boundary scan data register from tdi . once the new data has been shifted into the boundary scan data register, the data is saved in the parallel load registers when the tap controller enters the update dr state. this update of the parallel load register preloads data into the boundary scan data register that is associated with each input, output, and output enable. this preloaded data can be used with the extest and intest instructions to drive data into or out of the controller. please see ?boundary scan data register? on page 54 for more information. 5.4.1.4 abort instruction the abort instruction connects the associ ated abort data register chain between tdi and tdo . this instruction provides read and write a ccess to the abort register of the arm debug access port (dap). shifting the proper data into this data register clears various error bits or initiates a dap abort of a previous request. plea se see the ?abort data register? on page 55 for more information. 5.4.1.5 dpacc instruction the dpacc instruction connects the associated dpacc data register chain between tdi and tdo . this instruction provides read and write a ccess to the dpacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to the ar m debug and status registers. please see ?dpacc data register? on page 55 for more information. 5.4.1.6 apacc instruction the apacc instruction connects the associat ed apacc data register chain between tdi and tdo . this instruction provides read and write a ccess to the apacc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to inte rnal components and buses through the debug port. please see ?apacc data register? on page 55 for more information. 5.4.1.7 idcode instruction the idcode instruction connects the associ ated idcode data register chain between tdi and tdo . this instruction provides info rmation on the manufacturer, part number, and version of the arm core. this information can be used by te sting equipment and debuggers to automatically configure their input and output data streams. idco de is the default instruct ion that is loaded into the jtag instruction register when a power-on-reset (por) is asserted, trst is asserted, or the test-logic-reset state is entered. please see ?idcode data register? on page 54 for more information.
jtag interface 54 may 4, 2007 preliminary 5.4.1.8 bypass instruction the bypass instruction connects the associated bypass data register chain between tdi and tdo . this instruction is used to create a minimum length serial path between the tdi and tdo ports. the bypass data register is a single-bit sh ift register. this inst ruction improves test efficiency by allowing components that are not ne eded for a specific test to be bypassed in the jtag scan chain by loading th em with the bypass instructio n. please see ?bypass data register? on page 54 for more information. 5.4.2 data registers the jtag module contains six data register s. these include: id code, bypass, boundary scan, apacc, dpacc, and abort serial data regi ster chains. each of these data registers is discussed in the following sections. 5.4.2.1 idcode data register the format for the 32-b it idcode data register defined by the ieee standard 1149.1 is shown in figure 5-3. the standard requires that every jtag-compliant device implement either the idcode instruction or the bypass instruction as the default instruction. the lsb of the idcode data register is defined to be a 1 to distinguis h it from the bypass instru ction, which has an lsb of 0. this allows auto configuration test tool s to determine which instruction is the default instruction. the major uses of the jtag port are for ma nufacturer testing of component assembly, and program development and debug. to facilitate the use of auto- configuration de bug tools, the idcode instruction outputs a value of 0x1ba0 0477. this value indica tes an arm cortex-m3, version 1 processor. this allows the debuggers to automatically configur e themselves to work correctly with the cortex-m3 during debug. figure 5-3. idcode register format 5.4.2.2 bypass data register the format for the 1-bit bypass data register defined by the ieee standard 1149.1 is shown in figure 5-4. the standard requires that every jtag-compliant device implement either the bypass instruction or the idcode instruction as the de fault instruction. the lsb of the bypass data register is defined to be a 0 to distinguish it from the idco de instruction, which has an lsb of 1. this allows auto configuration test tool s to determine which instruction is the default instruction. figure 5-4. bypass register format 5.4.2.3 boundary scan data register the format of the boundary scan data register is shown in figure 5-5. each gpio pin, in a counter-clockwise direction from the jtag port pins, is included in the boundary scan data register. each gpio pin has three associated digita l signals that are included in the chain. these 1 version part number manufacturer id 0 1 11 12 27 28 31 tdo tdi 0 0 tdo tdi
lm3s817 data sheet may 4, 2007 55 preliminary signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. in addition to the gpio pins, the controller reset pin, rst , is included in the chain. because the reset pin is always an input, only the input signal is included in the data register chain. when the boundary scan data register is a ccessed with the sample/prel oad instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. the sampling of these values occurs on the rising edge of tck in the capture dr state of the tap controller. wh ile the sampled data is being shifted out of the boundary scan chain in the shift dr state of the tap controller, new data can be preloaded into the chain for use with the extest and intest instru ctions. these instructions either force data out of the controller, with the ext est instruction, or in to the controller, with the intest instruction. figure 5-5. boundary scan register format for detailed information on the order of the input, output, and output enable bits for each of the gpio ports, please refer to the stellaris family boundary scan description language (bsdl) files, downloadable from www.luminarymicro.com. 5.4.2.4 apacc data register the format for the 35-bit apacc data regi ster defined by arm is described in the arm? cortex?-m3 technical reference manual . 5.4.2.5 dpacc data register the format for the 35-bit dp acc data register defined by arm is described in the arm? cortex?-m3 technical reference manual . 5.4.2.6 abort data register the format for the 35-bit abort data regi ster defined by arm is described in the arm? cortex?-m3 technical reference manual . o tdo tdi o i ne u t o o i ne u t o o i ne u t o o i ne u t i n ... ... rst gpio pb6 gpio m gpio m+1 gpio n
system control 56 may 4, 2007 preliminary 6system control system control determines the overall operation of the device. it provides information about the device, controls the clocking of the device and in dividual peripherals, and handles reset detection and reporting. 6.1 functional description the system control module prov ides the following capabilities: ? device identification, see page 56 ? local control, such as reset (see page 56), power (see page 59) and clock control (see page 59) ? system control (run, sleep, and deep-sleep modes), see page 61 6.1.1 device identification seven read-only registers provide software with information on the microcontroller, such as version, part number, sram size, flas h size, and other features. see the did0 , did1 and dc0 - dc4 registers starting on page 64. 6.1.2 reset control this section discusses aspects of hardware fu nctions during reset as well as system software requirements following the reset sequence. 6.1.2.1 reset sources the controller has six sources of reset: 1. external reset input pin ( rst ) assertion, see page 56. 2. power-on reset (por), see page 57. 3. internal brown-out (bor) detector, see page 57. 4. software-initiated reset (with the software reset registers), see page 58. 5. a watchdog timer reset condition violation, see page 58. 6. internal low drop-out (ldo) regulator output, see page 59. after a reset, the reset cause (resc) register (see page 83) is set with the reset cause. the bits in this register are sticky and maintain their st ate across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the resc register are cleared. note: the main oscillator is used for external resets and power-on resets; the internal oscillator is used during the internal process by inte rnal reset and clock verification circuitry. 6.1.2.2 rst pin assertion the external reset pin ( rst ) resets the controller. this resets the core and all the peripherals except the jtag tap controller (see ?jtag interface? on page 46). the external reset sequence is as follows: 1. the external reset pin ( rst ) is asserted and then de-asserted. 2. after rst is de-asserted, the main crys tal oscillator must be allowed to settle and there is an internal main oscilla tor counter that ta kes from 15-30 ms to account for this. during this time, internal reset to the rest of the controller is held active.
lm3s817 data sheet may 4, 2007 57 preliminary 3. the internal reset is released and the controller fetches and loads the init ial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the external reset timing is shown in figure 19-8 on page 371. 6.1.2.3 power-on reset (por) the power-on reset (por) circuitry detects a ri se in power-supply voltage and generates an on-chip reset pulse. to use the on-chip circuitry, the rst input needs a pull-up resistor (1k to 10k ). the device must be operating within the specifie d operating parameters at the point when the on-chip power-on reset pulse is complete. the sp ecified operating parameters include supply voltage, frequency, temperature, and so on. if the operating conditions are not met at the point of por end, the stellaris controller does not operate correctly. in this ca se, the reset must be extended using external circuitry. the rst input may be used with the circuit as shown in figure 6-1. figure 6-1. external circuitry to extend reset the r 1 and c 1 components define the power-on delay. the r 2 resistor mitigates any leakage from the rst input. the diode discharges c 1 rapidly when the power supply is turned off. the power-on reset sequ ence is as follows: 1. the controller waits for the later of external reset ( rst ) or internal por to go inactive. 2. after the resets are inactive, the main crystal oscillator must be allowed to settle and there is an internal main oscilla tor counter that takes from 15-30 ms to account for this. during this time, internal reset to the rest of the controller is held active. 3. the internal reset is released and the controller fetches and loads the init ial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the internal por is only active on the initial power-up of th e controller. the power-on reset timing is shown in figure 19-9 on page 371. 6.1.2.4 brown-out reset (bor) a drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. this is initially disabled and may be enabled by software. the system provides a brown-out detection circuit that triggers if v dd drops below v bth . the circuit is provided to guard against improper opera tion of logic and peripherals that operate off v dd and not the ldo voltage. if a brown-out condition is detected, the system may generate a controller interrupt or a system re set. the bor circuit has a digital filter that protects against noise-related detection. this fe ature may be optionally enabled. r 1 c 1 r 2 rst stellaris d 1
system control 58 may 4, 2007 preliminary brown-out resets are controlled with the power-on and brown-out reset control (pborctl) register (see page 74). the borior bit in the pborctl register must be set for a brown-out to trigger a reset. the brown-out reset sequence is as follows: 1. when v dd drops below v bth , an internal bor condition is set. 2. if the borwt bit in the pborctl register is set, the bor co ndition is resa mpled sometime later (specified by bortim ) to determine if the original condition was caused by noise. if the bor condition is not met the second time, then no action is taken. 3. if the bor condition exists, an internal reset is asserted. 4. the internal reset is released and the controller fetches and loads the init ial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. 5. the internal bor signal is released after 500 s to pr event another bor condition from being set before software has a chance to investigate the original cause. the internal brown-out reset timing is shown in figure 19-10 on page 371. 6.1.2.5 software reset each peripheral can be reset by software. there ar e three registers that co ntrol this function (see the srcrn registers, starting on page 76). if the bit position corresponding to a peripheral is set, the peripheral is reset. the encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see ?system control? on page 61). writing a bit lane with a value of 1 initiates a reset of the corresponding unit. note that all reset signals for all clocks of the spec ified unit are asserted as a resu lt of a software-initiated reset. the entire system can be reset by software also. setting the sysresetreq bit in the cortex-m3 application interrupt and reset control register resets the entire system including the core. the software-initiated system reset sequence is as follows: 1. a software system reset in initiated by writing the sysresetreq bit in the arm cortex-m3 application interrupt and reset control register. 2. an internal reset is asserted. 3. the internal reset is released and the controller fetches and loads the init ial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the software-initiated system reset timing is shown in figure 19-11 on page 371. 6.1.2.6 watchdog timer reset the watchdog timer module's function is to pr event system hangs. the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. after the first time-out event, the 32-bit counter is reloaded with the value of the watchdog timer load (wdtload) register (see page 188), and the timer resumes counting down from that value. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog time r asserts its reset signal to the system. the watchdog timer reset sequence is as follows: 1. the watchdog timer times out for the second time without being serviced. 2. an internal reset is asserted.
lm3s817 data sheet may 4, 2007 59 preliminary 3. the internal reset is released and the controller fetches and loads the init ial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the watchdog reset timing is shown in figure 19-12 on page 372. 6.1.2.7 low drop-out a reset can be initiated when the internal low drop-out (ldo) regulator output goes unregulated. this is initially disabled and may be enab led by software. ldo is controlled with the ldo power control (ldopctl) register (see page 75). the ldo reset sequence is as follows: 1. ldo goes unregulated and the ldoarst bit in the ldoarst register is set. 2. an internal reset is asserted. 3. the internal reset is released and the controller fetches and loads the init ial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. the ldo reset timing is shown in figure 19-13 on page 372. 6.1.3 power control the ldo regulator permits the adjustment of the on-chip output voltage (v out ). the output may be adjusted in 50 mv increments between the range of 2.25 v through 2.75 v. the adjustment is made through the vadj field of the ldo power control (ldopctl) register (see page 75). 6.1.4 clock control system control determines the clocking and control of clocks in this part. 6.1.4.1 fundamental clock sources there are two fundamental clock sources for use in the device: ? the main oscillator, driven from either an external crystal or a single-ended source. as a crystal, the main oscillator source is specified to run from 1-8 mhz. however, when the crystal is being used as the pll source, it must be from 3.579545?8.192 mhz to meet pll requirements. as a single-ended source, the range is from dc to the specified speed of the device. ? the internal oscillator, which is an on-chip fr ee running clock. the internal oscillator is specified to run at 15 mhz 50%. it can be used to clock the system, but the tolerance of frequency range must be met. the internal system clock may be driven by either of the above two reference sources as well as the internal pll, provided that the pll input is connected to a clock source that meets its ac requirements. nearly all of the control for the clocks is provided by the run-mode clock configuration (rcc) register (see page 84). figure 6-2 shows the logic for the main clock tree . the peripheral blocks are driven by the system clock signal and can be programmatically en abled/disabled. the adc clock signal is automatically divided down to 14-18 mhz for prop er adc operation. the pwm clock signal is a synchronous divide by of the system clock to provide the pwm circuit with more range.
system control 60 may 4, 2007 preliminary figure 6-2. main clock tree 6.1.4.2 pll frequency configuration the user does not have direct control over the p ll frequency, but is required to match the external crystal used to an internal pll-crystal table. th is table is used to create the best fit for pll parameters to the crystal chosen. not all crystals result in the pll operating at exactly 200 mhz, though the frequency is within 1%. the result of the lookup is kept in the xtal to pll translation (pllcfg) register (see page 89). table 6-4 on page 88 describes the available crys tal choices and default programming of the pllcfg register. the crystal number is written into the xtal field of the run-mode clock configuration (rcc) register (see page 84). any time the xtal field changes, a read of the internal table is performed to get the correct value. table 6-4 on page 88 describes the available crystal choices and default programming values. 6.1.4.3 pll modes the pll has two modes of operation: normal and power-down ? normal: the pll multiplies the input clock reference and drives the output. ? power-down: most of the pll internal circuitry is disabled and the pll does not drive the output. the modes are programmed using the rcc register fields as shown in table 6-4 on page 88. 6.1.4.4 pll operation if the pll configuration is changed, the pll outp ut is not stable for a period of time (pll t ready =0.5 ms) and during this time, the pll is not usable as a clock reference. the pll is changed by one of the following: ? change to the xtal value in the rcc register (see page 84)?writes of the same value do not cause a relock. ? change in the pll from po wer-down to normal mode. a counter is defined to measure the t ready requirement. the counter is clocked by the main oscillator. the range of the main oscillator has been ta ken into account and the down counter is set to 0x1200 (that is, ~600 s at a 8.192-mhz external oscillator clock). hardware is provided to main osc 1-8 mhz internal osc 15 mhz 4 oscsrc a osc1 osc2 pll (200 mhz output ) bypass a sysdiv a usesysdiv a system clock constant divide (16 .667 m hz output ) adc clock pwmdiv a usepwmdiv a pwm clock oen a xtal a pwrdn a a. these are bit fields within the run-mode clock configuration (rcc) register.
lm3s817 data sheet may 4, 2007 61 preliminary keep the pll from being used as a system clock until the t ready condition is met after one of the two changes above. it is the user's responsibility to have a stabl e clock source (like the main oscillator) before the rcc register is switched to use the pll. 6.1.4.5 clock verification timers there are three identical clock veri fication circuits that can be enabled though software. the circuit checks the faster clock by a slower clock using timers: ? the main oscillator checks the pll. ? the main oscillator checks the internal oscillator. ? the internal oscillator divided by 64 checks the main oscillator. if the verification timer function is enabled and a failure is detected, the main clock tree is immediately switched to a working clock and an inte rrupt is generated to the controller. software can then determine the course of action to take. the actual failure indication and clock switching does not clear without a write to the clkvclr register, an external reset, or a por reset. the clock verification timers are controlled by the pllver , ioscver , and moscver bits in the rcc register (see page 84). 6.1.5 system control for power-savings purposes, the rcgcn , scgcn , and dcgcn registers control the clock gating logic for each peripheral or block in the system while the controller is in run, sleep, and deep-sleep mode, respectively. the dc1 , dc2 and dc4 registers act as a write mask for the rcgcn , scgcn , and dcgcn registers. in run mode, the controller is actively executing co de. in sleep mode, the clocking of the device is unchanged but the controller no long er executes code (and is no longer clocked). in deep-sleep mode, the clocking of the device may change (dep ending on the run mode clock configuration) and the controller no longer executes code (and is no longer clocked). an interrupt returns the device to run mode from one of the sleep modes; the sleep modes are entered on request from the code. each mode is described in more detail in this section. 6.1.5.1 run mode run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the rcgcn registers. the system clock can be any of the available clock sources including the pll. 6.1.5.2 sleep mode in sleep mode, the cortex-m3 processor core and the memory subsystem are not clocked. peripherals are clocked that are enabled in the scgcn register when auto clock gating is enabled (see rcc register on page 84) or the rcgcn register when the auto clock gating is disabled. the system clock has the same source and frequency as that during run mode. 6.1.5.3 deep-sleep mode the cortex-m3 processor core and the memory subsystem are not clocked. peripherals are clocked that are enabled in the dcgcn register when auto clock gating is enabled (see rcc register) or the rcgcn register when the auto clock gating is disabled. the system clock source is the main oscillator by default or the internal os cillator specified in the dslpclkcfg register if one is enabled (see page 95). when the dslpclkcfg register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. if the pll is running at the time of the wfi instruction, hardware powers the pll down and overrides the sysdiv field of the active rcc register to be /16 or /64 respectively. when the deep-sleep exit event occurs,
system control 62 may 4, 2007 preliminary hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode before enabling the clocks that were stopped during the deep-sleep duration. 6.2 initialization and configuration the pll is configured using di rect register writes to the run-mode clock configuration (rcc) register. the steps required to successfully change the pll-based system clock are: 1. bypass the pll and system clock divider by setting the bypass bit and clearing the usesys bit in the rcc register. this configures the system to run off a ?raw? clock source (using the main oscillator or in ternal oscillator) and allo ws for the new pll config uration to be validated before switching the syst em clock to the pll. 2. select the crystal value ( xtal ) and oscillator source ( oscsrc ), and clear the pwrdn and oen bits in rcc . setting the xtal field automatically pulls valid pll configuration data for the appropriate crystal, and clearing the pwrdn and oen bits powers and enables the pll and its output. 3. select the desired system divider ( sysdiv ) and set the usesys bit in rcc . the sysdiv field determines the system frequency for the microcontroller. 4. wait for the pll to lock by polling the plllris bit in the raw interrupt status (ris ) register. if the pll doesn?t lock, the configuration is invalid. 5. enable use of the pll by clearing the bypass bit in rcc . important: if the bypass bit is cleared before the pll locks, it is possible to render the device unusable. 6.3 register map table 6-1 lists the system control registers, grouped by function. the offset listed is a hexadecimal increment to the register?s address, relative to the system control base address of 0x400fe000. table 6-1. system control register map offset name reset type description see page device identificati on and capabilities 0x000 did0 - ro device identification 0 64 0x004 did1 - ro device identification 1 65 0x008 dc0 0x001f001f ro device capabilities 0 67 0x010 dc1 0x001133bf ro device capabilities 1 68 0x014 dc2 0x01070013 ro device capabilities 2 70 0x018 dc3 0x3f3f01ff ro device capabilities 3 71 0x01c dc4 0x0000001f ro device capabilities 4 73 local control 0x030 pborctl 0x00007ffd r/w power-on and brown-out reset control 74
lm3s817 data sheet may 4, 2007 63 preliminary 6.4 register descriptions the remainder of this section lists and describes the system control registers, in numerical order by address offset. 0x034 ldopctl 0x00000000 r/w ldo power control 75 0x040 srcr0 0x00000000 r/w software reset control 0 76 0x044 srcr1 0x00000000 r/w software reset control 1 77 0x048 srcr2 0x00000000 r/w software reset control 2 78 0x050 ris 0x00000000 ro raw interrupt status 79 0x054 imc 0x00000000 r/w interrupt mask control 80 0x058 misc 0x00000000 r/w1c masked interrupt status and clear 82 0x05c resc - r/w reset cause 83 0x060 rcc 0x078e3ac0 r/w run-mode clock configuration 84 0x064 pllcfg - ro xtal to pll translation 89 system control 0x100 rcgc0 0x00000000 r/w run-mode clock gating control 0 90 0x104 rcgc1 0x00000000 r/w run-mode clock gating control 1 92 0x108 rcgc2 0x00000000 r/w run-mode clock gating control 2 94 0x110 scgc0 0x00000001 r/w sleep-mode clock gating control 0 90 0x114 scgc1 0x00000000 r/w sleep-mode clock gating control 1 92 0x118 scgc2 0x00000000 r/w sleep-mode clock gating control 2 94 0x120 dcgc0 0x00000001 r/w deep-sleep-mode clock gating control 0 90 0x124 dcgc1 0x00000000 r/w deep-sleep-mode clock gating control 1 92 0x128 dcgc2 0x00000000 r/w deep-sleep-mode clock gating control 2 94 0x144 dslpclkcfg 0x07800000 r/w deep-sleep clock configuration 95 0x150 clkvclr 0x00000000 r/w clock verification clear 96 0x160 ldoarst 0x00000000 r/w allow unr egulated ldo to reset the part 97 table 6-1. system control register map (continued) offset name reset type description see page
system control 64 may 4, 2007 preliminary register 1: device identification 0 (did0), offset 0x000 this register identifies the version of the device. bit/field name type reset description 31 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 30:28 ver ro 0 this field defines the version of the did0 register format: 0=register version for the stellaris microcontrollers 27:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:8 major ro - this field specifies the major revision number of the device. the major revision number is indicated in the part number as a letter (a for first revision, b for second, and so on). this field is encoded as follows: 0: revision a (initial device) 1: revision b (first revision) and so on. 7:0 minor ro - this field specifies the minor revision number of the device. this field is numeric and is encoded as follows: 0: no changes. major revision was most recent update. 1: one interconnect change made since last major revision update. 2: two interconnect changes made since last major revision update. and so on. ro 0 device identification 0 (did0) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro - reset type --------------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved reserved minor ver major
lm3s817 data sheet may 4, 2007 65 preliminary register 2: device identification 1 (did1), offset 0x004 this register identifies the device family, pa rt number, temperature range, and package type. note: the bit diagram indicates some values are device-specific. the table below indicates values for your part. bit/field name type reset description 31:28 ver ro 0x0 this field defines the version of the did1 register format: 0=register version for the stellaris microcontrollers 27:24 fam ro 0x0 family this field provides the family identification of the device within the luminary micro product portfolio. the 0x0 value indicates the stellaris family of microcontrollers. 23:16 partno ro 0x36 part number this field provides the part number of the device within the family. the 0x36 value indicates the lm3s817 microcontroller. 15:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:5 temp ro 1 temperature range this field specifies the temper ature rating of the device. a value of 1 indicates the industrial temperature range (-40c to 85c). 4:3 pkg ro 0x1 this field specifies the package type. a value of 1 indicates a 48-pin lqfp package. 2 rohs ro 1 rohs-compliance a 1 in this bit specifies t he device is rohs-compliant. reserved ro 0 device identification 1 (did1) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 0000000- ------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000001011- - ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro qual ver pkg temp partno fam rohs
system control 66 may 4, 2007 preliminary 1:0 qual ro see table this field specifies the qualification stat us of the device. this field is encoded as follows: bit/field name type reset description qual description 00 engineering sample (unqualified) 01 pilot production (unqualified) 10 fully qualified 11 reserved
lm3s817 data sheet may 4, 2007 67 preliminary register 3: device capabilities 0 (dc0), offset 0x008 this register is predefined by the part and can be used to verify features. note: the bit diagram indicates the values are devic e-specific. the table below indicates values for your specific part. bit/field name type reset description 31:16 sramsz ro 0x001f indicates the size of the on-chip sram. a value of 0x001f indicates 8 kb of sram. 15:0 flshsz ro 0x001f indicates the size of the on-chip flash memory. a value of 0x001f indicates 64 kb of flash. ro - device capabilities register 0 (dc0) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type --------------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro - reset type --------------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro sramsz flshsz
system control 68 may 4, 2007 preliminary register 4: device capabilities 1 (dc1), offset 0x010 this register is predefined by the part and can be used to verify features. bit/field name type reset description 31:21 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 20 pwm a ro 1 a 1 in this bit indicates the presence of the pwm module. 19:17 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 16 adc a ro 1 a 1 in this bit indicates the presence of the adc module. 15:12 minsysdiv ro 0x03 the reset value is hardware-dependent. a value of 0x03 specifies a 50-mhz cpu clock with a pll divider of 4.see the rcc register (page 84) for how to change the system clock divisor using the sysdiv bit. 11:8 maxadcspd a ro 0x3 this field indicates the maximum rate at which the adc samples data. a value of 0x3 indicates 1m samples per second. 7 mpu ro 1 this bit indicates whether the memory protection unit (mpu) in the cortex-m3 is available. a 0 in this bit indicates the mpu is not available; a 1 indicates the mpu is available. see the arm? cortex?-m3 technical reference manual for details on the mpu. 6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 temp ro 1 this bit specifies the pr esence of an internal temperature sensor. 4 pll ro 1 a 1 in this bit indicates the presence of an implemented pll in the device. 3wdt a ro 1 a 1 in this bit indicates a watchdog timer on the device. ro 0 device capabilities 1 (dc1) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000010001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 011001110111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro pwm maxadcspd temp pll reserved adc minsysdiv wdt jtag swd swo mpu reserved reserved
lm3s817 data sheet may 4, 2007 69 preliminary 2swo a ro 1 a 1 in this bit indicates the presence of the arm serial wire output (swo) trace port capabilities. 1swd a ro 1 a 1 in this bit indicates the presence of the arm serial wire debug (swd) capabilities. 0jtag a ro 1 a 1 in this bit indicates the presence of a jtag port. a. these bits mask the run-mode clock gating control 0 (rcgc0) register (see page 113), sleep-mode clock gating control 0 (scgc0) register (see page 113), and deep-sleep-mode clock gating control 0 (dcgc0) register (see page 113). bits that are not noted are passed as 0. adcsp is clipped to the maximum value specified in dc1. bit/field name type reset description
system control 70 may 4, 2007 preliminary register 5: device capabilities 2 (dc2), offset 0x014 this register is predefined by the part and can be used to verify features. bit/field name type reset description 31:25 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 24 comp0 ro 1 a 1 in this bit indicates the presence of analog comparator 0. 23:19 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 18 gptm2 ro 1 a 1 in this bit indicates the presence of general-purpose timer module 2. 17 gptm1 ro 1 a 1 in this bit indicates the presence of general-purpose timer module 1. 16 gptm0 ro 1 a 1 in this bit indicates the presence of general-purpose timer module 0. 15:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 ssi ro 1 a 1 in this bit indicates the presence of the ssi module. 3:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 uart1 ro 1 a 1 in this bit indicates the presence of the uart1 module. 0 uart0 ro 1 a 1 in this bit indicates the presence of the uart0 module. reserved reserved reserved reserved ro 0 device capabilities 2 (dc2) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000100000111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000010011 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ssi comp0 gptm1 gptm0 uart0 gptm2 uart1
lm3s817 data sheet may 4, 2007 71 preliminary register 6: device capabilities 3 (dc3), offset 0x018 this register is predefined by the part and can be used to verify features. bit/field name type reset description 31:30 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 29 ccp5 ro 1 a 1 in this bit indicates the presence of the capture/ compare/pwm pin 5. 28 ccp4 ro 1 a 1 in this bit indicates the presence of the capture/ compare/pwm pin 4. 27 ccp3 ro 1 a 1 in this bit indicates the presence of the capture/ compare/pwm pin 3. 26 ccp2 ro 1 a 1 in this bit indicates the presence of the capture/ compare/pwm pin 2. 25 ccp1 ro 1 a 1 in this bit indicates the presence of the capture/ compare/pwm pin 1. 24 ccp0 ro 1 a 1 in this bit indicates the presence of the capture/ compare/pwm pin 0. 23:22 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 21 adc5 ro 1 a 1 in this bit indicates the presence of the adc5 pin. 20 adc4 ro 1 a 1 in this bit indicates the presence of the adc4 pin. 19 adc3 ro 1 a 1 in this bit indicates the presence of the adc3 pin. 18 adc2 ro 1 a 1 in this bit indicates the presence of the adc2 pin. 17 adc1 ro 1 a 1 in this bit indicates the presence of the adc1 pin. 16 adc0 ro 1 a 1 in this bit indicates the presence of the adc0 pin. 15:9 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 8 c0o ro 1 a 1 in this bit indicates the presence of the c0o pin. reserved reserved ro 0 device capabilities 3 (dc3) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 011111100111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ccp5 ccp4 ccp3 ccp2 ccp1 ccp0 adc5 adc4 adc3 adc2 adc1 adc0 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ro 0 reset type 000000111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro c0o c0+ c0- pwm5 pwm4 pwm3 pwm2 pwm1 pwm0
system control 72 may 4, 2007 preliminary 7 c0+ ro 1 a 1 in this bit indicates the presence of the c0+ pin. 6 c0- ro 1 a 1 in this bit indicates the presence of the c0- pin. 5 pwm5 ro 1 a 1 in this bit indicates the presence of the pwm5 pin. 4 pwm4 ro 1 a 1 in this bit indicates the presence of the pwm4 pin. 3 pwm3 ro 1 a 1 in this bit indicates the presence of the pwm3 pin. 2 pwm2 ro 1 a 1 in this bit indicates the presence of the pwm2 pin. 1 pwm1 ro 1 a 1 in this bit indicates the presence of the pwm1 pin. 0 pwm0 ro 1 a 1 in this bit indicates the presence of the pwm0 pin. bit/field name type reset description
lm3s817 data sheet may 4, 2007 73 preliminary register 7: device capabilities 4 (dc4), offset 0x01c this register is predefined by the part and can be used to verify features. bit/field name type reset description 31:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 porte ro 1 a 1 in this bit indicates the presence of gpio port e. 3 portd ro 1 a 1 in this bit indica tes the presence of gpio port d. 2 portc ro 1 a 1 in this bit indica tes the presence of gpio port c. 1 portb ro 1 a 1 in this bit indicates the presence of gpio port b. 0 porta ro 1 a 1 in this bit indicates the presence of gpio port a. ro 0 device capabilities 4 (dc4) offset 0x01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro porte portd portc portb porta reserved reserved
system control 74 may 4, 2007 preliminary register 8: power-on and brown-out reset control (pborctl), offset 0x030 this register is res ponsible for controlling reset condit ions after initial power-on reset. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:2 bortim r/w 0x1fff this field specifies t he number of internal oscillator clocks delayed before the bor output is resampled if the borwt bit is set. the width of this field is derived by the t bor width of 500 s and the internal oscillator (iosc) frequency of 15 mhz 50%. at +50%, the counter value has to exceed 10,000. 1 borior r/w 0 bor interrupt or reset this bit controls how a bor event is signaled to the controller. if set, a reset is signaled. otherwise, an interrupt is signaled. 0 borwt r/w 1 bor wait and check for noise this bit specifies the response to a brown-out signal assertion. if borwt is set to 1, the controller waits bortim iosc periods before resampling the bor output, and if asserted, it signals a bor condition interrupt or reset. if the bor resample is deasserted, the cause of the initial assertion was likely noise and the interrupt or reset is suppressed. if borwt is 0, bor assertions do not resample the output and any condition is reported immediately if enabled. ro 0 power-on and brown-out reset control (pborctl) offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 111111111111101 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved bortim borior borwt
lm3s817 data sheet may 4, 2007 75 preliminary register 9: ldo power control (ldopctl), offset 0x034 the vadj field in this register adjusts the on-chip output voltage (v out ) . bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:0 vadj r/w 0x0 this field sets the on-chip output voltage. the programming values for the vadj field are provided in table 6-2. table 6-2. vadj to v out vadj value v out (v) vadj value v out (v) vadj value v out (v) 0x1b 2.75 0x1f 2.55 0x03 2.35 0x1c 2.70 0x00 2.50 0x04 2.30 0x1d 2.65 0x01 2.45 0x05 2.25 0x1e 2.60 0x02 2.40 0x06-0x3f reserved ro 0 ldo power control (ldopctl) offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved reserved vadj
system control 76 may 4, 2007 preliminary register 10: software reset control 0 (srcr0), offset 0x040 writes to this register are masked by the bits in the device capabilities 1 (dc1) register (see page 68). bit/field name type reset description 31:21 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 20 pwm r/w 0 reset control for the pwm units. 19:17 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 16 adc r/w 0 reset control for the adc unit. 15:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 wdt r/w 0 reset control for the watchdog unit. 2:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved reserved ro 0 software reset control 0 (srcr0) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro ro r/w ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w ro ro ro reserved wdt pwm adc reserved
lm3s817 data sheet may 4, 2007 77 preliminary register 11: software reset control 1 (srcr1), offset 0x044 writes to this register are masked by the bits in the device capabilities 2 (dc2) register (see page 70). bit/field name type reset description 31:25 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 24 comp0 r/w 0 reset control for analog comparator 0. 23:19 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 18 gptm2 r/w 0 reset control for g eneral-purpose timer module 2. 17 gptm1 r/w 0 reset control for g eneral-purpose timer module 1. 16 gptm0 r/w 0 reset control for g eneral-purpose timer module 0. 15:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 ssi r/w 0 reset control for the ssi units. 3:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 uart1 r/w 0 reset control for the uart1 module. 0 uart0 r/w 0 reset control for the uart0 module. reserved reserved reserved reserved ro 0 software reset control 1 (srcr1) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro r/w ro ro ro ro ro r/w r/w r/w ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro r/w r/w ssi comp0 gptm1 gptm0 uart0 gptm2 uart1
system control 78 may 4, 2007 preliminary register 12: software reset control 2 (srcr2), offset 0x048 writes to this register are masked by the bits in the device capabilities 4 (dc4) register (see page 73). bit/field name type reset description 31:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 porte r/w 0 reset control for gpio port e. 3 portd r/w 0 reset control for gpio port d. 2 portc r/w 0 reset control for gpio port c. 1 portb r/w 0 reset control for gpio port b. 0 porta r/w 0 reset control for gpio port a. ro 0 software reset control (srcr2) offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w porte portd portc portb porta reserved reserved
lm3s817 data sheet may 4, 2007 79 preliminary register 13: raw interrupt st atus (ris), offset 0x050 central location for system control raw interrupts. these are set and cleared by hardware. bit/field name type reset description 31:7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 6 plllris ro 0 pll lock raw interrupt status this bit is set when the pll t ready timer asserts. 5 clris ro 0 current limit raw interrupt status this bit is set if the ldo?s cle output asserts. 4 iofris ro 0 internal oscillator fault raw interrupt status this bit is set if an internal oscillator fault is detected. 3 mofris ro 0 main oscillator fault raw interrupt status this bit is set if a main oscillator fault is detected. 2 ldoris ro 0 ldo power unregulated raw interrupt status this bit is set if a ldo voltage is unregulated. 1 borris ro 0 brown-out rese t raw interrupt status this bit is the raw interrupt status for any brown-out conditions. if set, a brown-out condition was detected. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. 0 pllfris ro 0 pll fault raw interrupt status this bit is set if a pll fault is detected (stops oscillating). ro 0 raw interrupt status (ris) offset 0x050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved plllris reserved clris iofris mofris ldoris borris pllfris
system control 80 may 4, 2007 preliminary register 14: interrupt mask control (imc), offset 0x054 central location for system control inte rrupt masks. bit/field name type reset description 31:7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 6 plllim r/w 0 pll lock interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrup t. if set, an interrupt is generated if plllris in ris is set; otherwise, an interrupt is not generated. 5 clim r/w 0 current li mit interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrup t. if set, an interrupt is generated if clris is set; otherwise, an interrupt is not generated. 4 iofim r/w 0 internal oscillator fault interrupt mask this bit specifies whether an internal oscillator fault detection is promoted to a cont roller interrupt. if set, an interrupt is generated if iofris is set; otherwise, an interrupt is not generated. 3 mofim r/w 0 main oscillator fault interrupt mask this bit specifies whether a main oscillator fault detection is promoted to a controller interrup t. if set, an interrupt is generated if mofris is set; otherwise, an interrupt is not generated. 2 ldoim r/w 0 ldo power unregulated interrupt mask this bit specifies whether an ldo unregulated power situation is promoted to a cont roller interrupt. if set, an interrupt is generated if ldoris is set; otherwise, an interrupt is not generated. ro 0 interrupt mask control (imc) offset 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w reserved plllim reserved clim iofim mofim ldoim borim pllfim
lm3s817 data sheet may 4, 2007 81 preliminary 1 borim r/w 0 brown-out reset interrupt mask this bit specifies whether a brown-out condition is promoted to a controller interrup t. if set, an interrupt is generated if borris is set; otherwise, an interrupt is not generated. 0 pllfim r/w 0 pll fault interrupt mask this bit specifies whether a pll fault detection is promoted to a controller interrupt. if set, an interrupt is generated if pllfris is set; otherwise, an interrupt is not generated. bit/field name type reset description
system control 82 may 4, 2007 preliminary register 15: masked interrupt status and clear (misc), offset 0x058 central location for system control result of ris and imc to gener ate an interrupt to the controller. all of the bits are r/w1c and this action also cl ears the corresponding raw interrupt bit in the ris register (see page 79). bit/field name type reset description 31:7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 6 plllmis r/w1c 0 pll lock masked interrupt status this bit is set when the pll t ready timer asserts. the interrupt is cleared by writing a 1 to this bit. 5 clmis r/w1c 0 current limi t masked interrupt status this bit is set if the ldo?s cle output asserts. the interrupt is cleared by writing a 1 to this bit. 4 iofmis r/w1c 0 internal oscillator fault masked interrupt status this bit is set if an internal oscillator fault is detected. the interrupt is cleared by writing a 1 to this bit. 3 mofmis r/w1c 0 main oscillator fault masked interrupt status this bit is set if a main oscillator fault is detected. the interrupt is cleared by writing a 1 to this bit. 2 ldomis r/w1c 0 ldo power unregulated masked interrupt status this bit is set if ldo power is unregulated. the interrupt is cleared by writing a 1 to this bit. 1 bormis r/w1c 0 brown-out reset masked interrupt status this bit is the masked interrupt status for any brown-out conditions. if set, a brown-out condition was detected. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. the interrupt is cleared by writing a 1 to this bit. 0 pllfmis r/w1c 0 pll faul t masked interrupt status this bit is set if a pll fault is detected (stops oscillating). the interrupt is cleared by writing a 1 to this bit. ro 0 masked interrupt status and clear (misc) offset 0x058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c reserved plllmis reserved clmis iofmis mofmis ldomis bormis pllfmis
lm3s817 data sheet may 4, 2007 83 preliminary register 16: reset cause (resc), offset 0x05c this field specifies the cause of the reset event to software. the reset value is determined by the cause of the reset. when an external reset is the cause ( ext is set), all other reset bits are cleared. however, if the reset is due to any ot her cause, the remaining bits are sticky, allowing software to see all causes. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 ldo r/w - when set to 1, ldo power ok lost is the cause of the reset event. 4 sw r/w - when set to 1, a software reset is the cause of the reset event. 3 wdt r/w - when set to 1, a watchdog reset is the cause of the reset event. 2 bor r/w - when set to 1, a brown-out reset is the cause of the reset event. 1 por r/w - when set to 1, a power-on reset is the cause of the reset event. 0 ext r/w - when set to 1, an external reset ( rst assertion) is the cause of the reset event. reserved ro 0 reset cause (resc) offset 0x05c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000- - - - - - ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved wdt bor por ext sw ldo
system control 84 may 4, 2007 preliminary register 17: run-mode clock configuration (rcc), offset 0x060 this register is defined to provide source control and frequency speed. bit/field name type reset description 31:28 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 27 acg r/w 0 auto clock gating this bit specifies whet her the system uses the sleep-mode clock gating control (scgcn) registers (see page 90) and deep-sleep-mode clock gating control (dcgcn) registers (see page 90) if the controller enters a sleep or deep-sleep mode (respectively). if set, the scgcn or dcgcn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. otherwise, the run-mode clock gating control (rcgcn) registers (see page 90) are us ed when the controller enters a sleep mode. the rcgcn registers are always used to control the clocks in run mode. this allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. ro 0 run-mode clock configuration (rcc) offset 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000011110001110 ro ro ro r/w r/w r/w r/w r/w r/w ro r/w r/w r/w r/w ro ro 0 reset type 011101011000000 ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro reserved reserved bypass oscsrc pllver sysdiv reserved pwrdn reserved acg usesysdiv usepwmdiv pwmdiv oen xtal ioscver moscver ioscdis moscdis
lm3s817 data sheet may 4, 2007 85 preliminary 26:23 sysdiv r/w 0xf system clock divisor specifies which divisor is used to generate the system clock from the pll output (200 mhz). when reading the run-mode clock configuration (rcc) register (see page 84), the sysdiv value is minsysdiv if a lower divider was requested and the pll is being used. this lower value is allowed to divide a non-pll source. 22 usesysdiv r/w 0 use the system clock divi der as the source for the system clock. the system clock divider is forced to be used when the pll is selected as the source. 21 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 20 usepwmdiv r/w 0 use the pwm clock di vider as the source for the pwm clock. bit/field name type reset description binary value divisor (bypass=1) frequency (bypass=0) 0000 reserved reserved 0001 /2 reserved 0010 /3 reserved 0011 /4 50 mhz 0100 /5 40 mhz 0101 /6 33.33 mhz 0110 /7 28.57 mhz 0111 /8 25 mhz 1000 /9 22.22 mhz 1001 /10 20 mhz 1010 /11 18.18 mhz 1011 /12 16.67 mhz 1100 /13 15.38 mhz 1101 /14 14.29 mhz 1110 /15 13.33 mhz 1111 /16 12.5 mhz (default)
system control 86 may 4, 2007 preliminary 19:17 pwmdiv r/w 0x7 pwm unit clock divisor this field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the pwm module. this clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. 16:14 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 13 pwrdn r/w 1 pll power down this bit connects to the pll pwrdn input. the reset value of 1 powers down the pll. see table 6-4 on page 88 for pll mode control. 12 oen r/w 1 pll output enable this bit specifies whether the pll output driver is enabled. if cleared, the driver transmits the pll clock to the output. otherwise, the pll clock does not oscillate outside the pll module. note: both pwrdn and oen must be cleared to run the pll. 11 bypass r/w 1 pll bypass chooses whether the system clo ck is derived from the pll output or the osc source. if se t, the clock that drives the system is the osc source. other wise, the clock that drives the system is the pll output clock divided by the system divider. note: the adc module must be clocked from the pll or directly from a 14-mhz to an 18-mhz clock source in order to operate properly. bit/field name type reset description value divisor 000 /2 001 /4 010 /8 011 /16 100 /32 101 /64 110 /64 111 /64 (default)
lm3s817 data sheet may 4, 2007 87 preliminary 10 pllver r/w 0 pll verification this bit controls the pll veri fication timer function. if set, the verification timer is enabled and an interrupt is generated if the pll becomes in operative. otherwise, the verification timer is not enabled. 9:6 xtal r/w 0xb this field specifies the crystal value attached to the main oscillator. the encoding for this field is provided in table 6-4 on page 88. oscillator-related bits 5:4 oscsrc r/w 0x0 picks among the four input sources for the osc. the values are: 3 ioscver r/w 0 this bit controls the in ternal oscillator verification timer function. if set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. otherwise, the verification timer is not enabled. 2 moscver r/w 0 this bit controls the main oscillator verification timer function. if set, the verification timer is enabled and an interrupt is generated if the timer becomes inoperative. otherwise, the verification timer is not enabled. 1 ioscdis r/w 0 internal oscillator disable 0: internal oscillator is enabled. 1: internal oscillator is disabled. 0 moscdis r/w 0 main oscillator disable 0: main oscillator is enabled. 1: main oscillator is disabled. table 6-3. pll mode control pwrdn oen mode 1 x power down 0 0 normal bit/field name type reset description value input source 00 main oscillator (default) 01 internal oscillator 10 internal oscillator / 4 (this is necessary if used as input to pll) 11 reserved
system control 88 may 4, 2007 preliminary table 6-4. default crystal field values and pll programming crystal number (xtal binary value) crystal frequency (mhz) 0000-0011 reserved 0100 3.579545 mhz 0101 3.6864 mhz 0110 4 mhz 0111 4.096 mhz 1000 4.9152 mhz 1001 5 mhz 1010 5.12 mhz 1011 6 mhz (reset value) 1100 6.144 mhz 1101 7.3728 mhz 1110 8 mhz 1111 8.192 mhz
lm3s817 data sheet may 4, 2007 89 preliminary register 18: xtal to pll translation (pllcfg), offset 0x064 this register provides a means of translating external crystal frequencies into the appropriate pll settings. this register is initialized during the reset sequence and updated anytime that the xtal field changes in the run-mode clock configuration (rcc) register (see page 84). bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:14 od ro - this field specifies the va lue supplied to the pll?s od input. 13:5 f ro - this field specifies the va lue supplied to the pll?s f input. 4:0 r ro - this field specifies the value supplied to the pll?s r input. ro 0 xtal to pll translation (pllcfg) offset 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro - reset type --------------- ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved r f od
system control 90 may 4, 2007 preliminary register 19: run-mode clock gating control 0 (rcgc0), offset 0x100 register 20: sleep-mode clock gating control 0 (scgc0), offset 0x110 register 21: deep-sleep-mode clock gating control 0 (dcgc0), offset 0x120 these registers control the cloc k gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the por ts necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register (see page 84) specifies that the system uses sleep modes. bit/field name type reset description 31:21 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 20 pwm r/w 0 this bit controls the clock gating for the pwm module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 19:17 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 16 adc r/w 0 this bit controls the clock gating for the adc module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 15:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. ro 0 run-mode, sleep-mode and deep-sleep-mode clock gating control 0 (rcgc0, scg0, and dcgc0) offset 0x100, 0x110, 0x120 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro ro r/w ro 0 reset type 000000000000000 ro ro ro r/w r/w r/w r/w ro ro ro ro r/w ro ro ro pwm maxadcspd reserved adc wdt reserved reserved reserved reserved
lm3s817 data sheet may 4, 2007 91 preliminary 11:8 maxadcspd r/w 0x0 this field sets the rate at which the adc samples data. you can set the sample rate by setting the maxadcspd bit as follows ( you cannot set the rate higher than the maximum rate. ): 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 wdt r/w 0 this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 2:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. a. if the unit is unclocked, a read or write to the unit generates a bus fault. bit/field name type reset description value sample rate 0x0 125k samples/second 0x1 250k samples/second 0x2 500k samples/second 0x3 1m samples/second
system control 92 may 4, 2007 preliminary register 22: run-mode clock gating control 1 (rcgc1), offset 0x104 register 23: sleep-mode clock gating control 1 (scgc1), offset 0x114 register 24: deep-sleep-mode clock gating control 1 (dcgc1), offset 0x124 these registers control the cloc k gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the por ts necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register (see page 84) specifies that the system uses sleep modes. bit/field name type reset description 31:25 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 24 comp0 r/w 0 this bit controls the clock gating for the comparator 0 module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 23:19 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 18 gptm2 r/w 0 this bit controls the cl ock gating for the general purpose timer 2 module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 17 gptm1 r/w 0 this bit controls the cl ock gating for the general purpose timer 1 module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 16 gptm0 r/w 0 this bit controls the cl ock gating for the general purpose timer 0 module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a reserved reserved reserved reserved ro 0 run-mode, sleep-mode, and deep-sleep-mode clock gating control 1 (rcgc1, scgc1, and dcgc1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro r/w ro ro ro ro ro r/w r/w r/w ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w ro ro r/w r/w ssi comp0 gptm2 gptm1 gptm0 uart1 uart0 offset 0x104, 0x114, and 0x124
lm3s817 data sheet may 4, 2007 93 preliminary 15:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 ssi r/w 0 this bit controls the clo ck gating for the ssi module. if set, the unit receives a clock and f unctions. otherwise, the unit is unclocked and disabled. a 3:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 uart1 r/w 0 this bit controls the cl ock gating for the uart1 module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 0 uart0 r/w 0 this bit controls the cl ock gating for the uart0 module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a a. if the unit is unclocked, reads or wr ites to the unit will generate a bus fault. bit/field name type reset description
system control 94 may 4, 2007 preliminary register 25: run-mode clock gating control 2 (rcgc2), offset 0x108 register 26: sleep-mode clock gating control 2 (scgc2), offset 0x118 register 27: deep-sleep-mode clock gating control 2 (dcgc2), offset 0x128 these registers control the cloc k gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the por ts necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register (see page 84) specifies that the system uses sleep modes. bit/field name type reset description 31:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 porte r/w 0 this bit controls the clock gating for the gpio port e module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 3 portd r/w 0 this bit controls the clock gating for the gpio port d module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 2 portc r/w 0 this bit controls the clock gating for the gpio port c module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a a. if the unit is unclocked, reads or wr ites to the unit will generate a bus fault. 1 portb r/w 0 this bit controls the clock gating for the gpio port b module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a 0 porta r/w 0 this bit controls the clock gating for the gpio port a module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. a ro 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w porte portd portc portb porta reserved reserved run-mode, sleep-mode, and deep-sleep-mode clock gating control 2 (rcgc2, scgc2, and dcgc2) offset 0x108, 0x118, and 0x128
lm3s817 data sheet may 4, 2007 95 preliminary register 28: deep-sleep clock configuration (dslpclkcfg), offset 0x144 this register is used to automatic ally switch from the main oscillato r to the internal oscillator when entering deep-sleep mode. the syst em clock source is the main oscillator by default. when this register is set, the inte rnal oscillator is power ed up and the main oscillato r is powered down. when the deep-sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 iosc r/w 0 this field allows an override of the main oscillator when deep-sleep mode is running. when set, this field forces the internal oscillator to be the clock source during deep-sleep mode. otherwise, the main osc illator remains as the default system clock source. ro 0 deep-sleep clock configuration (dslpclkcfg) offset 0x144 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w iosc reserved reserved
system control 96 may 4, 2007 preliminary register 29: clock verification clear (clkvclr), offset 0x150 this register is provided as a means of clearing the clock verification circuits by software. since the clock verification circuits force a known good clock to control the process, the controller is allowed the opportunity to solve the problem and clear the verification fault. this register clears all clock verification faults. to clear a clock verification fault, the verclr bit must be set and then cleared by software. this bit is not self-clearing. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 verclr r/w 0 clear clock verification faults. ro 0 clock verification clear (clkvclr) offset 0x150 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w verclr reserved reserved
lm3s817 data sheet may 4, 2007 97 preliminary register 30: allow unregulated ldo to reset the part (ldoarst), offset 0x160 this register is provided as a means of allowi ng the ldo to reset the pa rt if the voltage goes unregulated. use this register to choose whether to automatically reset th e part if the ldo goes unregulated, based on the design tolerance for ldo fluctuation. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 ldoarst r/w 0 set to 1 to allow unregulated ldo output to reset the part. ro 0 allow unregulated ldo to reset the part (ldoarst) offset 0x160 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w ldoarst reserved reserved
internal memory 98 may 4, 2007 preliminary 7 internal memory the lm3s817 microcontroller comes with 8 kb of bit-banded sram and 64 kb of flash memory. the flash controller provides a user-friendly inte rface, making flash programming a simple task. flash protection can be applied to th e flash memory on a 2-kb block basis. 7.1 block diagram figure 7-1. flash block diagram 7.2 functional description this section describes the functionality of both memories. 7.2.1 sram memory the internal sram of the stellaris devices is located at address 0x 20000000 of the device memory map. to reduce the number of time consuming read-modify-wri te (rmw) operations, arm has introduced bit - banding technology in the new cortex-m3 processor. with a bit-band-enabled processor, certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. flash control fma fcmisc fcim fcris fmc fmd flash timing usecrl flash protection fmpre fmppe flash array sram array bridge cortex-m3 icode dcode system bus apb
lm3s817 data sheet may 4, 2007 99 preliminary the bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) for example, if bit 3 at address 0x20001000 is to be modified, the bit-band alias is calculated as: 0x22000000 + (0x1000 * 32) + (3 * 4) = 0x2202000c with the alias address calculated, an instruction performing a read/write to address 0x2202000c allows direct access to only bit 3 of the byte at address 0x20001000. for details about bit-banding, please refer to chapter 4, ?memory map? in the arm? cortex?-m3 technical reference manual . 7.2.2 flash memory the flash is organized as a set of 1-kb blocks th at can be individually erased. erasing a block causes the entire contents of the block to be rese t to all 1s. these blocks are paired into a set of 2-kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only, providing different levels of code protection. read-only blocks cannot be erased or programmed, protecting the conten ts of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 7.2.2.1 flash memory timing the timing for the flash is automatic ally handled by the flash controller. however, in order to do so, it must know the clock rate of t he system in order to time its internal signals properly. the number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. it is software's responsibility to keep th e flash controller updated with this information via the usec reload (usecrl) register (see page 106). on reset, usecrl is loaded with a value that configures the flash timing so t hat it works with the default crystal value of 6 mhz. if software ch anges the system operating frequency, the new operating frequency must be loaded into usecrl before any flash modifications are attempted. for example, if the device is operating at a spe ed of 20 mhz, a value of 0x13 must be written to the usecrl register. 7.2.2.2 flash memory protection the user is provided two forms of flash prot ection per 2-kb flash blocks in two 32-bit wide registers. the protection policy for each form is controlled by individual bits (per policy per block) in the fmppe (see page 105) and fmpre registers (see page 104). ? flash memory protection program enable (fmppe[blockn:block0]) : if set, the block may be programmed (written) or erased. if cleared, the block may not be changed. ? flash memory protection read enable (fmpre[blockn:block0]) : if set, the block may be executed or read by software or debuggers. if cleared, the block may only be executed. the contents of the memory block are prohibited from being accessed as data and traversing the dcode bus.
internal memory 100 may 4, 2007 preliminary the policies may be combined as shown in table 7-1. an access that attempts to program or erase a pe-protected block is prohibited. a controller interrupt may be optionally generated (by setting the amask bit in the fim register) to alert software developers of poorly behaving softwa re during the development and debug phases. an access that attempts to read an re-protected block is prohibited. such accesses return data filled with all 0s. a contro ller interrupt may be optionally generat ed to alert softwa re developers of poorly behaving software during the development and debug phases. the factory settings for the fmpre and fmppe registers are a value of 1 for all implemented banks. this implements a policy of open access and programmability. the register bits may be changed by writing the specific register bit. t he changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. 7.2.2.3 flash protection by disabling debug access flash memory may also be protected by permanent ly disabling access to the debug access port (dap) through the jtag and swd interfaces. this is accomplished by clearing the dbg field of the fmpre register. flash memory protection read enable (dbg field): if set to 0x2, access to the dap is enabled through the jtag and swd interfaces. if clear, access to the dap is disabled. the dbg field programming becomes permanent, and irreversible, after a commit sequence is performed. in the initial state, provided from the factory, access is enabl ed in order to facilitate code development and debug. access to the dap may be disabled at the end of the manufacturing flow, once all tests have passed and software loaded. this change will not take effect until the next power-up of the device. note that it is recommended that disabling access to the dap be combined with a mechanism for providing end-user installable updates (if necessary) such as the stellaris boot loader. important: once the dbg field is cleared and committed, this field can never be restored to the factory-programmed value?which means jtag/swd interface to the debug module can never be re-enabled. this sequence does not disable the jtag controller, it only disables the access of the dap through the jtag or swd interfaces. the jtag interface remains functional and access to the test access port remains enabled, allowing the user to execute the ieee jtag-defined in structions (for example, to perform boundary scan operations). table 7-1. flash protection policy combinations fmppe fmpre protection 00 execute-only protection. the block may only be executed and may not be written or erased. this mode is used to protect code. 10 the block may be written, erased, or executed, but not read. this combination is unlikely to be used. 01 read-only protection. the block may be read or executed but may not be written or erased. this mode is used to lock the block from further modification while allowing any read or execute access. 11 no protection. the block may be written, erased, executed, or read.
lm3s817 data sheet may 4, 2007 101 preliminary if the user will also be using the fmpre bits to protect flash memory from being read as data (to mark sets of 2 kb blocks of flash memory as execute-only), these one-time-programmable bits should be written at the same time that the de bug disable bits are programmed. mechanisms to execute the one-time code sequence to disable all debug access include: ? selecting the debug disable option in the stellaris boot loader ? loading the debug disable sequence into sram and running it once from sram after programming the final end application code into flash 7.2.2.4 flash memory programming writing the flash memory requires that the code be executed out of sram to avoid corrupting or interrupting the bus timing. flash pages can be erased on a page basis (1 kb in size), or by performing a mass erase of the entire flash. all erase and program operations are performed using the flash memory address (fma) , flash memory data (fmd) and flash memory control (fmc) registers. see section 7.3 for examples. 7.3 initialization and configuration this section shows examples for using the flash controller to perform various operations on the contents of the flash memory. 7.3.1 changing flash protection bits as discussed in section 7.2.2.2, changes to the protection bits must be committed before they take effect. the sequence below is used c hange and commit a block protection bit in the fmpre or fmppe registers. the sequence to change and commit a bit in software is as follows: 1. the flash memory protection read enable (fmpre) and flash memory protection program enable (fmppe) registers are written, changing the intended bit(s). the action of these changes can be tested by software while in this state. 2. the flash memory address (fma) register (see page 107) bit 0 is set to 1 if the fmppe register is to be committed; otherwise, a 0 commits the fmpre register. 3. the flash memory control (fmc) register (see page 110) is written with the comt bit set. this initiates a write sequence and commits the changes. there is a special sequence to change and commit the dbg bits in the flash memory protection read enable (fmpre) register. this sequence also sets and commits any changes from 1 to 0 in the block protection bits (for execute-only) in the fmpre register. 1. 1. the flash memory protection read enable (fmpre) register is written, changing the intended bit(s). the action of th ese changes can be tested by software while in this state. 2. 2. the flash memory address (fma) register (see page 102) is written with a value of 0x900. 3. 3. the flash memory control (fmc) register (see page 104) is written with the comt bit set. this initiates a write sequence and commits the changes. below is an example code sequence to permanently disable the jtag and swd interface to the debug module using luminary micro's driverlib peripheral driver library: #include "hw_types.h" #include "hw_flash.h" void permanently_disable_jtag_swd(void) {
internal memory 102 may 4, 2007 preliminary // // clear the dbg field of the fmpre register. note that the value // used in this instance does not affect the state of the blockn // bits, but were the value different, all bits in the fmpre are // affected by this function! // hwreg(flash_fmpre) &= 0x3fffffff; // // the following sequence activates the one-time // programming of the fmpre register. // hwreg(flash_fma) = 0x900; hwreg(flash_fmc) = (flash_fmc_wrkey | flash_fmc_comt); // // wait until the operation is complete. // while (hwreg(flash_fmc) & flash_fmc_comt) { } } 7.3.2 flash programming the stellaris devices provide a user-friendly in terface for flash programming. all erase/program operations are handled via three registers: fma , fmd and fmc . the flash is programmed using the following sequence: 1. write source data to the fmd register. 2. write the target address to the fma register. 3. write the flash write key and the write bit (a value of 0xa4420001) to the fmc register. 4. poll the fmc register until the write bit is cleared. to perform an erase of a 1-kb page: 1. write the page address to the fma register. 2. write the flash write key and the erase bit (a value of 0xa4420002) to the fmc register. 3. poll the fmc register until the erase bit is cleared. to perform a mass erase of the flash: 1. write the flash write key and the merase bit (a value of 0xa4420004) to the fmc register. 2. poll the fmc register until the merase bit is cleared. 7.4 register map table 7-2 lists the flash memory and control r egisters. the offset listed is a hexadecimal increment to the register?s address, relative to the flash control base address of 0x400fd000,
lm3s817 data sheet may 4, 2007 103 preliminary except for fmpre and fmppe , which are relative to the system control base address of 0x400fe000. 7.5 register descriptions the remainder of this section lists and describes the flash memory registers, in numerical order by address offset. table 7-2. flash register map offset name reset type description see page 0x130 a a. relative to system control base address of 0x400fe000. fmpre 0xffffffff r/w0 flash memory read protect 104 0x134 a fmppe 0xffffffff r/w0 flash me mory program protect 105 0x140 a usecrl 0x00000031 r/w usec reload 106 0x000 fma 0x00000000 r/w flash memory address 107 0x004 fmd 0x00000000 r/w flash memory data 109 0x008 fmc 0x00000000 r/w flash memory control 110 0x00c fcris 0x00000000 ro flash controller raw interrupt status 112 0x010 fcim 0x00000000 r/w flash controller interrupt mask 113 0x014 fcmisc 0x00000000 r/w1c flash controller masked interrupt status and clear 114
internal memory 104 may 4, 2007 preliminary register 1: flash memory protection read enable (fmpre), offset 0x130 note: offset is relative to system control base address of 0x400fe000 this register stores the read-only ( fmpre ) protection bits for each 2-kb flash block and bits to disable debug access through jtag and swd. this register is loaded during the power-on reset sequence. the factory setting for the fmpre register is a value of 1 for all implemented flash banks and 0x2 for the dbg field. these bits implement a po licy of open access, prog rammability, and debug access. the register bits may be changed by writing the specific register bit. however, this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the last 4 kb of flash (from 60 kb to 64 kb) will always be readable as both code and data. however, this region can still be wr ite-protected through the use of the fmppe register. the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see ?flash memory protection? on page 87. bit/field name type reset description 31:30 dbg r/w0 0x2 controls access to the debug access port (dap) through the jtag and swd interfaces. a value of 0x2 enables access. a value of 0 disables access. 29:0 block29- block0 r/w0 0x3fffffff enable 2-kb flash blocks to be executed or read. the policies may be combined as shown in table 7-1 on page 100. r/w0 r/w0 r/w0 r/w0 1111 block0 block1 block2 block3 r/w0 r/w0 r/w0 r/w0 1111 block4 block5 block6 block7 r/w0 r/w0 r/w0 r/w0 1111 block8 block9 block10 block11 r/w0 r/w0 r/w0 r/w0 1111 block12 block13 block14 block15 r/w0 r/w0 r/w0 r/w0 1111 block15 block17 block18 block19 r/w0 r/w0 r/w0 r/w0 1111 block20 block21 block22 block23 r/w0 r/w0 r/w0 r/w0 1111 block24 block25 block26 block27 r/w0 r/w0 r/w0 r/w0 1011 block28 block29 dbg flash memory protection read enable (fmpre) offset 0x130 and 0x134 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type reset type
lm3s817 data sheet may 4, 2007 105 preliminary register 2: flash memory protection program enab le (fmppe), of fset 0x134 note: offset is relative to system control base address of 0x400fe000 this register stores the execute-only ( fmppe ) protection bits for each 2-kb flash block. this register is loaded during the power-on reset sequence. the factory setting for the fmppe register is a value of 1 for all implemented banks. this implements a policy of open acce ss and programmability. the regi ster bits may be changed by writing the specific register bit. however, this register is r/ w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see ?flash memory protection? on page 99. bit/field name type reset description 31:0 block31- block0 r/w0 1 enable 2-kb flash blocks to be written or erased ( fmppe register). this policy may be combined with the fmpre register as shown in table 7-1 on page 100. reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0000000000000000 reserved ro ro ro ro ro ro r/w0 r/w0 r/w0 r/w0 ro ro 00000000 1111 block0 block1 block2 block3 r/w0 r/w0 r/w0 r/w0 1111 block4 block5 block6 block7 flash memory protection program enable (fmppe) offset 0x130 and 0x134 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type reset type r/w0 r/w0 r/w0 r/w0 1111 block0 block1 block2 block3 r/w0 r/w0 r/w0 r/w0 1111 block4 block5 block6 block7 r/w0 r/w0 r/w0 r/w0 1111 block8 block9 block10 block11 r/w0 r/w0 r/w0 r/w0 1111 block12 block13 block14 block15 r/w0 r/w0 r/w0 r/w0 1111 block15 block17 block18 block19 r/w0 r/w0 r/w0 r/w0 1111 block20 block21 block22 block23 r/w0 r/w0 r/w0 r/w0 1111 block24 block25 block26 block27 r/w0 r/w0 r/w0 r/w0 1111 block28 block29 block30 block31 flash memory protection program enable (fmppe) offset 0x130 and 0x134 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type reset type
internal memory 106 may 4, 2007 preliminary register 3: usec reload (usecrl), offset 0x140 note: offset is relative to system control base address of 0x400fe000 this register is provided as a means of creati ng a 1-s tick divider reload value for the flash controller. the internal flash has specific mini mum and maximum requirements on the length of time the high voltage write pulse can be applied. it is required that this register contain the operating frequency (in mhz -1) whenever the flas h is being erased or programmed. the user is required to change this value if the clocking conditions are changed for a flash erase/program operation. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 usec r/w 0x31 mhz -1 of the controller clock when the flash is being erased or programmed. usec should be set to 0x31 (49 mhz) whenever the flash is being erased or programmed. ro 0 usec reload (usecrl) offset 0x140 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000110001 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w usec reserved reserved
lm3s817 data sheet may 4, 2007 107 preliminary register 4: flash memory address (fma), offset 0x000 during a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. during erase operations, this register contains a 1 kb-aligned address and
internal memory 108 may 4, 2007 preliminary specifies which page is erased. note that the alig nment requirements must be met by software or the results of the operation are unpredictable. bit/field name type reset description 31:16 reserved ro 0x0 reserved bits return an indeterminate value, and should never be changed. 15:0 offset r/w 0x0 address offset in flash where operation is performed. ro 0 flash memory address (fma) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved offset reserved ro 0 flash memory address (fma) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved offset reserved ro 0 flash memory address (fma) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved offset reserved ro 0 flash memory address (fma) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved offset
lm3s817 data sheet may 4, 2007 109 preliminary register 5: flash memory data (fmd), offset 0x004 this register contains the data to be written during the programming cycle or read during the read cycle. note that the contents of this register ar e undefined for a read access of an execute-only block. this register is not used during the erase cycles. bit/field name type reset description 31:0 data r/w 0x0 data value for write operation. 0 flash memory data (fmd) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w data data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
internal memory 110 may 4, 2007 preliminary register 6: flash memory control (fmc), offset 0x008 when this register is written, the flash controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 107). if the access is a write access, the data contained in the flash memory data (fmd) register (see page 109) is written. this is the final register written and initiates the memory operation. there are four control bits in the lower byte of this register that, when set, initiate the memory operation. the most used of these register bits are the erase and write bits. it is a programming error to write multiple contro l bits and the results of such an operation are unpredictable. bit/field name type reset description 31:16 wrkey wo 0x0 this field contains a write key, which is used to minimize the incidence of accidental flash writes. the value 0xa442 must be written into this field for a write to occur. writes to the fmc register without this wrkey value are ignored. a read of this field returns the value 0. 15:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 comt r/w 0 commit (write) of register value to nonvolatile storage. a write of 0 has no effect on the state of this bit. if read, the state of the previous commit access is provided. if the previous commit access is complete, a 0 is returned; otherwise, if the commit acce ss is not complete, a 1 is returned. this can take up to 50 s. 2 merase r/w 0 mass erase flash memory if this bit is set, the flash ma in memory of the device is all erased. a write of 0 has no effe ct on the state of this bit. if read, the state of the pr evious mass erase access is provided. if the previous mass erase access is complete, a 0 is returned; otherwise, if t he previous mass erase access is not complete, a 1 is returned. this can take up to 250 ms. reserved wo 0 flash memory control (fmc) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w comt wrkey merase erase write
lm3s817 data sheet may 4, 2007 111 preliminary 1 erase r/w 0 erase a page of flash memory if this bit is set, the page of flash main memory as specified by the contents of fma is erased. a write of 0 has no effect on the state of this bit. if read, the state of the previous erase access is provided. if the previous erase access is complete, a 0 is returned; otherwise, if the previous er ase access is not complete, a 1 is returned. this can take up to 25 ms. 0 write r/w 0 write a word into flash memory if this bit is set, the data stored in fmd is written into the location as specified by the contents of fma . a write of 0 has no effect on the state of this bit. if read, the state of the previo us write update is provided. if the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. this can take up to 50 s. bit/field name type reset description
internal memory 112 may 4, 2007 preliminary register 7: flash controller raw inte rrupt status (fcris), offset 0x00c this register indicates that the flash controller has an interrupt co ndition. an inte rrupt is only signaled if the corresponding fcim register bit is set. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pris ro 0 programming raw interrupt status this bit indicates the curr ent state of the programming cycle. if set, the programmi ng cycle completed; if cleared, the programming cycle has no t completed. programming cycles are either write or erase actions generated through the flash memory control (fmc) register bits (see page 110). 0 aris ro 0 access raw interrupt status this bit indicates if the flash was improperly accessed. if set, the program tried to access the flash counter to the policy as set in the flash memory protection read enable (fmpre) and flash memory protection program enable (fmppe) registers (see page 104). otherwise, no access has tried to improperly access the flash. reserved ro 0 flash controller raw interrupt status (fcris) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro aris reserved pris
lm3s817 data sheet may 4, 2007 113 preliminary register 8: flash controller interrupt mask (fcim), offset 0x010 this register controls whether the flash cont roller generates interrupts to the controller. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pmask r/w 0 programming interrupt mask this bit controls the repo rting of the programming raw interrupt status to th e controller. if set, a programming-generated interrupt is promoted to the controller. otherwise, interrupts are recorded but suppressed from the controller. 0 amask r/w 0 access interrupt mask this bit controls the reporting of the access raw interrupt status to the controller. if set, an access-generated interrupt is promoted to the controller. otherwise, interrupts are recorded but suppressed from the controller. reserved ro 0 flash controller interrupt mask (fcim) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w amask reserved pmask
internal memory 114 may 4, 2007 preliminary register 9: flash controller masked interrupt status and clear (fcmisc), offset 0x014 this register provides two functions. first, it re ports the cause of an interrupt by indicating which interrupt source or sources are signaling the interrup t. second, it serves as the method to clear the interrupt reporting. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pmisc r/w1c 0 programming masked interrupt status and clear this bit indicates whether an interrupt was signaled because a programming cycl e completed and was not masked. this bit is cleared by writing a 1. the pris bit in the fcris register (see page 112) is also cleared when the pmisc bit is cleared. 0 amisc r/w1c 0 access masked interrupt status and clear this bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. this bit is cleared by writing a 1. the aris bit in the fcris register is also cleared when the amisc bit is cleared. reserved ro 0 flash controller masked interrupt status and clear (fcmisc) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c amisc reserved pmisc
lm3s817 data sheet may 4, 2007 115 preliminary 8 general-purpose input/outputs (gpios) the gpio module is composed of five physical gpio blocks, each corresponding to an individual gpio port (port a, port b, port c, port d, and port e). the gpio module is firm-compliant and supports 1 to 30 programmable input/output pins, depending on the peripherals being used. the gpio module has the following features: ? programmable control for gpio interrupts: ? interrupt gene ration masking ? edge-triggered on risi ng, falling, or both ? level-sensitive on high or low values ? 5-v-tolerant input/outputs ? bit masking in both read and write operations through address lines ? programmable control for gpio pad configuration: ? weak pull-up or pull-down resistors ? 2-ma, 4-ma, and 8-ma pad drive ? slew rate control for the 8-ma drive ? open drain enables ? digital input enables
general-purpose input/outputs (gpios) 116 may 4, 2007 preliminary 8.1 block diagram figure 8-1. gpio module block diagram 8.2 functional description important: all gpio pins are inputs by default ( gpiodir =0 and gpioafsel =0), with the exception of the five jtag pins ( pb7 and pc[3:0] . the jtag pins default to their jtag functionality ( gpioafsel =1). asserting a power- on-reset (por) or an external reset ( rst ) puts both groups of pins back to their default state. each gpio port is a separate hardware instantiat ion of the same physical block (see figure 8-2). the lm3s817 microcontroller contains five ports and thus five of these physical gpio blocks. u0rx u0t x ssiclk gpio port a uart0 ssifss ssirx ssitx ssi pa0 pa1 pa2 pa3 pa4 pa5 gpio port b pwm2 pwm3 fault pwm1 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 c0- c0o c0+ analog comparators gpio port c pc0 pc1 pc2 pc3 tck/swclk tms/swdio tdi tdo/swo jtag swd/swo trst ccp4 ccp5 gp timer 2 pc4 pc5 pc6 pc7 gpio port d pd0 pd1 pd2 pd3 pd4 pd5 pwm0 pwm1 ccp0 gp timer 0 ccp1 ccp2 gp timer 1 ccp3 gpio block e pe0 pe1 pwm4 pwm5 fault pwm2 fault pwm0 lm3 s817 uart1 u1rx u1tx
lm3s817 data sheet may 4, 2007 117 preliminary figure 8-2. gpio port block diagram 8.2.1 data register operation to aid in the efficiency of software, the gpio ports allow for the modification of individual bits in the gpio data (gpiodata) register (see page 123) by using bits [9:2] of the address bus as a mask. this allows software drivers to mo dify individual gpio pins in a single instruction, without affecting the state of the other pins. this is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual gp io pin. to accommodate this feature, the gpiodata register covers 256 locations in the memory map. during a write, if the address bit associated with that data bit is set to 1, the value of the gpiodata register is altered. if it is cleared to 0, it is left unchanged. for example, writing a value of 0xeb to the addr ess gpiodata + 0x098 would yield as shown in figure 8-3, where u is data unchanged by the write. gpioibe gpiois gpioim gpioiev gpiomis gpioris gpioicr interrupt control gpiodr4r gpiodr2r gpioslr gpiodr8r gpiopdr gpiopur gpioden gpioodr i/o pad control gpioafsel function selection gpiodir gpiodata i/o data m u x m u x d e m u x i/o pad alternate input alternate output alternate output enable interrupt gpio input gpio output gpio output enable pad input pad output pad output enable package i/o pin gpioperiphid0 identification registers gpioperiphid1 gpioperiphid2 gpioperiphid3 gpioperiphid4 gpioperiphid5 gpioperiphid6 gpioperiphid7 gpiopcellid0 gpiopcellid1 gpiopcellid2 gpiopcellid3
general-purpose input/outputs (gpios) 118 may 4, 2007 preliminary figure 8-3. gpiodata write example during a read, if the address bit associated with t he data bit is set to 1, the value is read. if the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. for example, reading address gpiodata + 0x0c4 yields as shown in figure 8-4. figure 8-4. gpiodata read example 8.2.2 data direction the gpio direction (gpiodir) register (see page 124) is used to configure each individual pin as an input or output. 8.2.3 interrupt operation the interrupt capabilities of each gpio port are controlled by a set of seven registers. with these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. when one or more gpio inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire gpio port . for edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. for a level-sensit ive interrupt, it is assumed that the external source holds the level consta nt for the interrup t to be recognized by the controller. three registers are required to define the edge or sense that causes interrupts: ? gpio interrupt sense (gpiois) register (see page 125) ? gpio interrupt both edges (gpioibe) register (see page 126) ? gpio interrupt event (gpioiev) register (see page 127) interrupts are enabled/disabled via the gpio interrupt mask (gpioim) register (see page 128). when an interrupt condition occurs, the state of th e interrupt signal can be viewed in two locations: the gpio raw interrupt status (gpioris) and gpio masked interrupt status (gpiomis) registers (see pages 129 and 130). as the name implies, the gpiomis register only shows interrupt conditions that are allowed to be passed to the controller. the gpioris register indicates that a gpio pin meets the conditio ns for an interrupt, but has no t necessarily been sent to the controller. 0xeb gpiodata 0x098 1 1 1 0 0 1 1 1 u 1 u u 0 u 1 u 1 7 0 6 4 5 3 2 addr[9:2] 9 7 8 6 4 5 3 21 0 0 1 0 0 1 0 1 0 0 0 returned value 0 1 0 1 0 0 0 0 7 5 6 4 2 3 1 0 addr[9:2] 9 7 8 6 4 5 3 210 1 1 gpiodata 1 1 0 1 1 0 0x0c4 0 1 0 1 0 0 0 1 0 0
lm3s817 data sheet may 4, 2007 119 preliminary in addition to providing gpio functionality, pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin ( gpioim is set to 1), not only is an interrupt for portb generated, but an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger, an adc conversion is initiated. if no other portb pins are being used to generate interrupts, the arm integrated nested vectored interrupt controller (nvic) interrupt set enable (setna) register can disable the portb interrupts and the adc interrupt can be used to read back the converted data. otherwise, the portb interrupt handler needs to ignore and clear interrupts on b4, and wait for the adc interrupt or the adc interrupt needs to be disabled in the setna regi ster and the portb interrupt handler polls the adc registers until the conversion is completed. interrupts are cleared by writing a 1 to the gpio interrupt clear (gpioicr) register (see page 131). when programming interrupts, the interrupts should be masked ( gpioim set to 0). writing any value to an interrup t control register ( gpiois , gpioibe , or gpioiev ) can generate a spurious interrupt if the corresponding bits are enabled. 8.2.4 mode control the gpio pins can be controlled by either hardware or software. when hardware control is enabled via the gpio alternate function select (gpioafsel) register (see page 132), the pin state is controlled by its alternate function (that is , the peripheral). software control corresponds to gpio mode, where the gpiodata register is used to read/write the corresponding pins. 8.2.5 pad configuration the pad configuration registers allow for gpio pad configuration by software based on the application requirements. the pad co nfiguration registers include the gpiodr2r , gpiodr4r , gpiodr8r , gpioodr , gpiopur , gpiopdr , gpioslr , and gpioden registers. 8.2.6 identification the identification registers configured at reset a llow software to detect and identify the module as a gpio block. the identification registers include the gpioperiphid0 - gpioperiphid7 registers as well as the gpiopcellid0 - gpiopcellid3 registers. 8.3 initialization and configuration to use the gpio, the peripheral clock must be enabled by setting porta , portb , portc , portd , and porte in the rcgc2 register. on reset, all gpio pins (except for the five jtag pins) default to general-purpose input mode ( gpiodir and gpioafsel both set to 0). table 8-1 shows all possible configurations of the
general-purpose input/outputs (gpios) 120 may 4, 2007 preliminary gpio pads and the control register settings re quired to achieve them. table 8-2 shows how a rising edge interrupt would be conf igured for pin 2 of a gpio port. table 8-1. gpio pad configuration examples configuration register bit value a a. x=ignored (don?t care bit) ?=can be either 0 or 1, depending on the configuration gpioafsel gpiodir gpioodr gpioden gpiopur gpiopdr gpiodr2r gpiodr4r gpiodr8r gpioslr digital input (gpio) 0 0 0 1 ? ?xxxx digital output (gpio) 0101?????? open drain input (gpio) 0 0 1 1xxxxxx open drain output (gpio) 0111xx???? digital input (timer ccp) 1x0 1 ? ?xxxx digital output (pwm) 1x01?????? digital output (timer pwm) 1x01?????? digital input/output (ssi) 1x01?????? digital input/output (uart) 1x01?????? analog input (comparator) 0 0 0 0 0 0xxxx digital output (comparator) 1x01?????? table 8-2. gpio interrupt configuration example register desired interrupt event trigger pin 2 bit value a a. x=ignored (don?t care bit) 7 6 5 4 3 2 1 0 gpiois 0=edge 1=level xxxxx0xx gpioibe 0=single edge 1=both edges xxxxx0xx gpioiev 0=low level, or negative edge 1=high level, or positive edge xxxxx1xx gpioim 0=masked 1=not masked 00000100
lm3s817 data sheet may 4, 2007 121 preliminary 8.4 register map table 8-2 lists the gpio registers. the offset lis ted is a hexadecimal increment to the register?s address, relative to that gpio port?s base address: ? gpio port a: 0x40004000 ? gpio port b: 0x40005000 ? gpio port c: 0x40006000 ? gpio port d: 0x40007000 ? gpio port e: 0x40024000 important: the gpio registers in this chapter are duplicated in each gpio block, however, depending on the block, all eight bits may not be connected to a gpio pad (see figure 8-1 on page 116). in those cases, wr iting to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. table 8-3. gpio register map offset name reset type description see page 0x000 gpiodata 0x00000000 r/w data 123 0x400 gpiodir 0x00000000 r/w data direction 124 0x404 gpiois 0x00000000 r/ w interrupt sense 125 0x408 gpioibe 0x00000000 r/w i nterrupt both edges 126 0x40c gpioiev 0x00000000 r/w interrupt event 127 0x410 gpioim 0x00000000 r/w i nterrupt mask enable 128 0x414 gpioris 0x00000000 ro raw interrupt status 129 0x418 gpiomis 0x00000000 ro masked interrupt status 130 0x41c gpioicr 0x00000000 w1c interrupt clear 131 0x420 gpioafsel see note a r/w alternate function select 132 0x500 gpiodr2r 0x000000ff r/w 2-ma drive select 133 0x504 gpiodr4r 0x00000000 r/w 4-ma drive select 134 0x508 gpiodr8r 0x00000000 r/w 8-ma drive select 135 0x50c gpioodr 0x00000000 r/w open drain select 136 0x510 gpiopur 0x000000ff r/w pull-up select 137 0x514 gpiopdr 0x00000000 r/w pull-down select 138 0x518 gpioslr 0x00000000 r/w slew rate control select 139 0x51c gpioden 0x000000ff r/w digital input enable 140 0xfd0 gpioperiphid4 0x00000000 ro pe ripheral identification 4 141
general-purpose input/outputs (gpios) 122 may 4, 2007 preliminary 8.5 register descriptions the remainder of this section lists and describes the gpio registers, in numerical order by address offset. 0xfd4 gpioperiphid5 0x00000000 ro pe ripheral identification 5 142 0xfd8 gpioperiphid6 0x00000000 ro pe ripheral identification 6 143 0xfdc gpioperiphid7 0x00000000 ro pe ripheral identification 7 144 0xfe0 gpioperiphid0 0x00000061 ro pe ripheral identification 0 145 0xfe4 gpioperiphid1 0x00000000 ro pe ripheral identification 1 146 0xfe8 gpioperiphid2 0x00000018 ro pe ripheral identification 2 147 0xfec gpioperiphid3 0x00000001 ro pe ripheral identification 3 148 0xff0 gpiopcellid0 0x0000000d ro gpio primecell identification 0 149 0xff4 gpiopcellid1 0x000000f0 ro gpio primecell identification 1 150 0xff8 gpiopcellid2 0x00000005 ro gpio primecell identification 2 151 0xffc gpiopcellid3 0x000000b1 ro gpio primecell identification 3 152 a. the default reset value for the gpioafsel register is 0x00000000 for all gpio pins, with the exception of the five jtag pins ( pb7 and pc[3:0] . these five pins default to jtag functionality. because of this, the default reset value of gpioafsel for gpio port b is 0x00000080 while t he default reset value of gpioafsel for port c is 0x0000000f. table 8-3. gpio register map (continued) offset name reset type description see page
lm3s817 data sheet may 4, 2007 123 preliminary register 1: gpio data (gpiodata), offset 0x000 the gpiodata register is the data register. in software control mode, values written in the gpiodata register are transferred onto the gpio por t pins if the respective pins have been configured as outputs through the gpio direction (gpiodir) register (see page 124). in order to write to gpiodata , the corresponding bits in the mask, resulting from the address bus bits [9:2], must be high. otherwise, the bit values remain unchanged by the write. similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. bits that are 1 in the address mask cause the corresponding bits in gpiodata to be read, and bits that are 0 in the address mask cause the corresponding bits in gpiodata to be read as 0, regardless of their value. a read from gpiodata returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the correspo nding input pin when these are configured as inputs. all bits are cleared by a reset. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 data r/w 0 gpio data this register is virtually mapped to 256 locations in the address space. to facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are ma sked by the eight address lines ipaddr[9:2] . reads from this regist er return its current state. writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. see ?data register operation? on page 117 for examples of reads and writes. reserved ro 0 gpio data (gpiodata) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved data
general-purpose input/outputs (gpios) 124 may 4, 2007 preliminary register 2: gpio direction (gpiodir), offset 0x400 the gpiodir register is the data direction register. bits set to 1 in the gpiodir register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. all bits are cleared by a reset, meaning all gpio pins are inputs by default. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 dir r/w 0x00 gpio data direction 0: pins are inputs. 1: pins are outputs. reserved ro 0 gpio direction (gpiodir) offset 0x400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved dir
lm3s817 data sheet may 4, 2007 125 preliminary register 3: gpio interrupt sense (gpiois), offset 0x404 the gpiois register is the interrupt sens e register. bits set to 1 in gpiois configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. all bits are cleared by a reset. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 is r/w 0x00 gpio interrupt sense 0: edge on corresponding pin is detected (edge-sensitive). 1: level on corresponding pin is detected (level-sensitive). reserved ro 0 gpio interrupt sense (gpiois) offset 0x404 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved is
general-purpose input/outputs (gpios) 126 may 4, 2007 preliminary register 4: gpio interrupt both edges (gpioibe), offset 0x408 the gpioibe register is the interrupt both-edges re gister. when the corresponding bit in the gpio interrupt sense (gpiois) register (see page 125) is set to detect edges, bits set to high in gpioibe configure the corresponding pi n to detect both rising and falling edges, rega rdless of the corresponding bit in the gpio interrupt event (gpioiev) register (see page 127). clearing a bit configures the pin to be controlled by gpioiev . all bits are cleared by a reset. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ibe r/w 0x00 gpio in terrupt both edges 0: interrupt generation is controlled by the gpio interrupt event (gpioiev) register (see page 142). 1: both edges on the corresponding pin trigger an interrupt. note: single edge is determined by the corresponding bit in gpioiev . reserved ro 0 gpio interrupt both edges (gpioibe) offset 0x408 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved ibe
lm3s817 data sheet may 4, 2007 127 preliminary register 5: gpio interrupt event (gpioiev), offset 0x40c the gpioiev register is the interrupt event register. bits set to high in gpioiev configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the gpio interrupt sense (gpiois) register (see page 125). clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in gpiois . all bits are cleared by a reset. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 iev r/w 0x00 gpio interrupt event 0: falling edge or low levels on corresponding pins trigger interrupts. 1: rising edge or high levels on corresponding pins trigger interrupts. reserved ro 0 gpio interrupt event (gpioiev) offset 0x40c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved iev
general-purpose input/outputs (gpios) 128 may 4, 2007 preliminary register 6: gpio interrupt mask (gpioim), offset 0x410 the gpioim register is the interrupt mask register. bits set to high in gpioim allow the corresponding pins to trigger their individual interrupts and the combined gpiointr line. clearing a bit disables interrupt triggering on that pin. all bits are cleared by a reset. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ime r/w 0x00 gpio interrupt mask enable 0: corresponding pin interrupt is masked. 1: corresponding pin interrupt is not masked. reserved ro 0 gpio interrupt mask (gpioim) offset 0x410 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved ime
lm3s817 data sheet may 4, 2007 129 preliminary register 7: gpio raw interrupt status (gpioris), offset 0x414 the gpioris register is the raw interrupt status register. bits read high in gpioris reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the gpio interrupt mask (gpioim) register (see page 128). bits read as ze ro indicate that corresponding input pins have not initiated an interrupt. all bits are cleared by a reset. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ris ro 0x00 gpio interrupt raw status reflect the status of interrupt trigger condition detection on pins (raw, prior to masking). 0: corresponding pin interrupt requirements not met. 1: corresponding pin interrupt has met requirements. reserved ro 0 gpio raw interrupt status (gpioris) offset 0x414 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved ris
general-purpose input/outputs (gpios) 130 may 4, 2007 preliminary register 8: gpio masked interrupt status (gpiomis), offset 0x418 the gpiomis register is the masked interrupt status register. bits read high in gpiomis reflect the status of input lines triggering an interrupt. bits read as low indicate that either no interrupt has been generated, or the interrupt is masked. in addition to providing gpio functionality, pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin ( gpioim is set to 1), not only is an interrupt for portb generated, but an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register (see page 219) is configured to use the external trigger, an adc conversion is initiated. if no other portb pins are being used to generate interrupts, the arm integrated nested vectored interrupt controller (nvic) interrupt set enable (setna) register can disable the portb interrupts and the adc interrupt can be used to read back the converted data. otherwise, the portb interrupt handler needs to ignore and clear interrupts on b4, and wait for the adc interrupt or the adc interrupt needs to be disabled in the setna regi ster and the portb interrupt handler polls the adc registers until the conversion is completed. gpiomis is the state of the interrupt after masking. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 mis ro 0x00 gpio masked interrupt status masked value of interrupt due to corresponding pin. 0: corresponding gpio line interrupt not active. 1: corresponding gpio line asserting interrupt. reserved ro 0 gpio masked interrupt status (gpiomis) offset 0x418 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved mis
lm3s817 data sheet may 4, 2007 131 preliminary register 9: gpio interrupt clear (gpioicr), offset 0x41c the gpioicr register is the interrupt clear register. writ ing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. writing a 0 has no effect. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ic w1c 0x00 gpio interrupt clear 0: corresponding interrupt is unaffected. 1: corresponding interrupt is cleared. reserved ro 0 gpio interrupt clear (gpioicr) offset 0x41c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro w1c w1c w1c w1c w1c w1c w1c w1c reserved ic
general-purpose input/outputs (gpios) 132 may 4, 2007 preliminary register 10: gpio alternate function select (gpioafsel), offset 0x420 the gpioafsel register is the mode control select regist er. writing a 1 to any bit in this register selects the hardware control for the corresponding gpio line. all bits are cleared by a reset, therefore no gpio line is set to hardware control by default. caution ? all gpio pins are inputs by defa ult (gpiodir=0 and gpioafsel=0), with the exception of the five jtag pins ( pb7 and pc[3:0] ). the jtag pins default to their jtag functionality (gpioafsel=1). asserting a power-on-reset (por) or an external reset ( rst ) puts both groups of pins back to their default state. if the jtag pins are used as gpios in a design, pb7 and pc2 cannot have external pull-down resistors connected to both of them at the same ti me. if both pins are pulled low during reset, the controller has unpredictable behavior. if this happens, remove one or both of the pull-down resistors, and apply rst or power-cycle the part. in addition, it is possible to create a software sequence that prevents the debugger from connecting to the stellaris microcontroller. if the program code loaded into flash immediately changes the jtag pins to their gpio functionality, the debugger may not have enough time to connect and halt the controller before the jtag pin functionality switches. this may lock the debugger out of the part. this can be avoided with a software routin e that restores jtag functionality based on an external or software trigger. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 afsel r/w see note gpio alternate function select 0: software control of corres ponding gpio line (gpio mode). 1: hardware control of corresponding gpio line (alternate hardware function). note: the default reset value for the gpioafsel register is 0x00 for all gpio pins, with the exception of the five jtag pins ( pb7 and pc[3:0] ). these five pins default to jtag functionalit y. because of this, the default reset value of gpioafsel for gpio port b is 0x80 while the default reset value of gpioafsel for port c is 0x0f. reserved ro 0 gpio alternate function select (gpioafsel) offset 0x420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000- - - - - - - - ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved afsel
lm3s817 data sheet may 4, 2007 133 preliminary register 11: gpio 2-ma drive select (gpiodr2r), offset 0x500 the gpiodr2r register is the 2-ma drive control register . it allows for each gpio signal in the port to be individually configured without affecting the other pads. when writing a drv2 bit for a gpio signal, the corresponding drv4 bit in the gpiodr4r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 drv2 r/w 0xff output pad 2-ma drive enable a write of 1 to either gpiodr4 [n] or gpiodr8 [n] clears the corresponding 2-ma enable bit. the change is effective on the second clock cycle after the write. reserved ro 0 gpio 2-ma drive select (gpiodr2r) offset 0x500 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011111111 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved drv2
general-purpose input/outputs (gpios) 134 may 4, 2007 preliminary register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 the gpiodr4r register is the 4-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing the drv4 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 drv4 r/w 0x00 output pad 4-ma drive enable a write of 1 to either gpiodr2 [n] or gpiodr8 [n] clears the corresponding 4-ma enable bit. the change is effective on the second clock cycle after the write. reserved ro 0 gpio 4-ma drive select (gpiodr4r) offset 0x504 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved drv4
lm3s817 data sheet may 4, 2007 135 preliminary register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 the gpiodr8r register is the 8-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing the drv8 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv4 bit in the gpiodr4r register are automatically cleared by hardware. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 drv8 r/w 0x00 output pad 8-ma drive enable a write of 1 to either gpiodr2 [n] or gpiodr4 [n] clears the corresponding 8-ma enable bit. the change is effective on the second clock cycle after the write. reserved ro 0 gpio 8-ma drive select (gpiodr8r) offset 0x508 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved drv8
general-purpose input/outputs (gpios) 136 may 4, 2007 preliminary register 14: gpio open drain select (gpioodr), offset 0x50c the gpioodr register is the open drain control register. setting a bit in this register enables the open drain configuration of the corresponding gp io pad. when open drain mode is enabled, the corresponding bit should also be set in the gpio digital input enable (gpioden) register (see page 140). corresponding bits in the drive strength registers ( gpiodr2r , gpiodr4r , gpiodr8r , and gpioslr ) can be set to achieve the desired rise and fall times. the gpio acts as an open drain input if the corresponding bit in the gpiodir register is set to 0; and as an open drain output when set to 1. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 ode r/w 0x00 output p ad open drain enable 0: open drain config uration is disabled. 1: open drain config uration is enabled. reserved ro 0 gpio open drain select (gpioodr) offset 0x50c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved ode
lm3s817 data sheet may 4, 2007 137 preliminary register 15: gpio pull-up se lect (gpiopur), offset 0x510 the gpiopur register is the pull-up control register. when a bit is set to 1, it enables a weak pull-up resistor on the corresponding gpio signal. setting a bit in gpiopur automatically clears the corresponding bit in the gpio pull-down select (gpiopdr) register (see page 138). bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pue r/w 0xff pad weak pull-up enable a write of 1 to gpiopdr [n] clears the corresponding gpiopur [n] enables. the change is effective on the second clock cycle after the write. reserved ro 0 gpio pull-up select (gpiopur) offset 0x510 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011111111 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved pue
general-purpose input/outputs (gpios) 138 may 4, 2007 preliminary register 16: gpio pull-down select (gpiopdr), offset 0x514 the gpiopdr register is the pull-down control register. when a bit is set to 1, it enables a weak pull-down resistor on the corresponding gpio signal. setting a bit in gpiopdr automatically clears the corresponding bit in the gpio pull-up select (gpiopur) register (see page 137). bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pde r/w 0x00 pad weak pull-down enable a write of 1 to gpiopur [n] clears the corresponding gpiopdr [n] enables. the change is effective on the second clock cycle after the write. reserved ro 0 gpio pull-down select (gpiopdr) offset 0x514 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved pde
lm3s817 data sheet may 4, 2007 139 preliminary register 17: gpio slew rate control select (gpioslr), offset 0x518 the gpioslr register is the slew rate control register. slew rate control is only available when using the 8-ma drive strength option via the gpio 8-ma drive select (gpiodr8r) register (see page 135). bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 srl r/w 0 slew rate limit enable (8-ma drive only) 0: slew rate control disabled. 1: slew rate control enabled. reserved ro 0 gpio slew rate control select (gpioslr) offset 0x518 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved srl
general-purpose input/outputs (gpios) 140 may 4, 2007 preliminary register 18: gpio digital input enable (gpioden), offset 0x51c the gpioden register is the digital input enable r egister. by default, all gpio signals are configured as digital inputs at reset. the only time that a pin should not be configured as a digital input is when the gpio pin is configured to be one of the analog input signals for the analog comparator. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 den r/w 0xff digital-input enable 0: digital input disabled 1: digital input enabled reserved ro 0 gpio digital input enable (gpioden) offset 0x51c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011111111 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved den
lm3s817 data sheet may 4, 2007 141 preliminary register 19: gpio peripheral identifi cation 4 (gpioperiphid4), offset 0xfd0 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 gpio peripheral id register[7:0] reserved ro 0 gpio peripheral identification 4 (gpioperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
general-purpose input/outputs (gpios) 142 may 4, 2007 preliminary register 20: gpio peripheral identifi cation 5 (gpioperiphid5), offset 0xfd4 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 gpio periph eral id register[15:8] reserved ro 0 gpio peripheral identification 5 (gpioperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
lm3s817 data sheet may 4, 2007 143 preliminary register 21: gpio peripheral identifi cation 6 (gpioperiphid6), offset 0xfd8 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 gpio peripher al id register[23:16] reserved ro 0 gpio peripheral identification 6 (gpioperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
general-purpose input/outputs (gpios) 144 may 4, 2007 preliminary register 22: gpio peripheral identifi cation 7 (gpioperiphid7), offset 0xfdc the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 gpio peripher al id register[31:24] reserved ro 0 gpio peripheral identification 7 (gpioperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
lm3s817 data sheet may 4, 2007 145 preliminary register 23: gpio peripheral identifi cation 0 (gpioperiphid0), offset 0xfe0 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x61 gpio peripheral id register[7:0] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 0 (gpioperiphid0) offset 0xfe0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000001100001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
general-purpose input/outputs (gpios) 146 may 4, 2007 preliminary register 24: gpio peripheral identifi cation 1(gpioperiphid1), offset 0xfe4 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x00 gpio peripheral id register[15:8] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 1 (gpioperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
lm3s817 data sheet may 4, 2007 147 preliminary register 25: gpio peripheral identifi cation 2 (gpioperiphid2), offset 0xfe8 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 gpio peripheral id register[23:16] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 2 (gpioperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
general-purpose input/outputs (gpios) 148 may 4, 2007 preliminary register 26: gpio peripheral identifi cation 3 (gpioperiphid3), offset 0xfec the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; ea ch register contains eight bits of the 32-bit register, used by software to identify the peripheral. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x01 gpio peripheral id register[31:24] can be used by software to identify the presence of this peripheral. reserved ro 0 gpio peripheral identification 3 (gpioperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
lm3s817 data sheet may 4, 2007 149 preliminary register 27: gpio primec ell identification 0 (gpi opcellid0), offset 0xff0 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d gpio primecell id register[7:0] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 0 (gpiopcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
general-purpose input/outputs (gpios) 150 may 4, 2007 preliminary register 28: gpio primec ell identification 1 (gpi opcellid1), offset 0xff4 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 gpio primec ell id register[15:8] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 1 (gpiopcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
lm3s817 data sheet may 4, 2007 151 preliminary register 29: gpio primec ell identification 2 (gpi opcellid2), offset 0xff8 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 gpio primec ell id register[23:16] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 2 (gpiopcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
general-purpose input/outputs (gpios) 152 may 4, 2007 preliminary register 30: gpio primec ell identification 3 (gpi opcellid3), offset 0xffc the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. the register is used as a standard cross-peripheral identification system. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 gpio primec ell id register[31:24] provides software a standard cross-peripheral identification system. reserved ro 0 gpio primecell identification 3 (gpiopcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
lm3s817 data sheet may 4, 2007 153 preliminary 9 general-purpose timers programmable timers can be used to count or time external events that drive the timer input pins. the lm3s817 controller general-purpose timer module (gptm) contains three gptm blocks (timer0, timer1, and timer 2). each gptm block provides two 16-bit timer/counters (referred to as timera and timerb) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-b it timer or one 32-bit real-time clock (rtc). timers can also be used to trigger analog-to-digita l (adc) conversions. the trigger signals from all of the general-purpose timers are ored together before reaching the adc module, so only one timer should be used to trigger adc events. the general-purpose timer module is one timing resource available on the stellaris microcontrollers. other timer resources include the system timer (systick) (see ?system timer (systick)? on page 36) and the pwm timer in the pwm module (see ?pwm timer? on page 320). the following modes are supported: ? 32-bit timer modes: ? programmable one-shot timer ? programmable periodic timer ? real-time clock using 32.768-khz input clock ? software-controlled event stalling (excluding rtc mode) ? 16-bit timer modes: ? general-purpose timer function with an 8-bit prescaler ? programmable one-shot timer ? programmable periodic timer ? software-controlle d event stalling ? 16-bit input capture modes: ? input edge count capture ? input edge time capture ? 16-bit pwm mode: ? simple pwm mode with software-programma ble output inversion of the pwm signal
general-purpose timers 154 may 4, 2007 preliminary 9.1 block diagram figure 9-1. gptm module block diagram 9.2 functional description the main components of each gptm block are two free-running 16-bit up/down counters (referred to as timera and timerb), two 16-bit match regi sters, two prescaler match registers, and two 16-bit load/initialization registers and their associat ed control functions. t he exact functionality of each gptm is controlled by software and configured through the register interface. software configures the gptm using the gptm configuration (gptmcfg) register (see page 165), the gptm timera mode (gptmtamr) register (see page 166), and the gptm timerb mode (gptmtbmr) register (see page 167). when in on e of the 32-bit modes, the timer can only act as a 32-bit timer. however, when configured in 16-bit mode, the gptm can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 gptm reset conditions after reset has been applied to the gptm module, the module is in an inactive state, and all control registers are cleared and in their default states. counters timera and timerb are initialized to 0xffff, along with their corresponding load registers: the gptm timera interval load (gptmtailr) register (see page 175) and the gptm timerb interval load (gptmtbilr) register (see page 176). the prescale counters are initialized to 0x00: the gptm timera prescale (gptmtapr) register (see page 179) and the gptm timerb prescale (gptmtbpr) register (see page 180). 9.2.2 32-bit timer operating modes note: both the odd- and even-numbered ccp pins are used for 16-bit mode. only the even-numbered ccp pins are used for 32-bit mode. ta comparator tb comparator gptmtbr gptmar clock / edge detect rtc divider clock / edge detect timera interrupt timerb interrupt system clock 0x0000 (down counter modes ) 0x0000 (down counter modes ) ccp (even) ccp (odd) en en timera control gptmtapmr gptmtailr gptmtamatchr gptmtapr gptmtamr timerb control gptmtbpmr gptmtbilr gptmtbmatchr gptmtbpr gptmtbmr interrupt / config gptmcfg gptmris gptmicr gptmmis gptmimr gptmctl
lm3s817 data sheet may 4, 2007 155 preliminary this section describes the three gptm 32-bit timer modes (one-shot, periodic, and rtc) and their configuration. the gptm is placed into 32-bit mode by writi ng a 0 (one-shot/periodic 32-bit timer mode) or a 1 (rtc mode) to the gptm configuration (gptmcfg) register. in both configurations, certain gptm registers are concatenated to form pseu do 32-bit registers. these registers include: ? gptm timera interval load (gptmtailr) register [15:0], see page 175 ? gptm timerb interval load (gptmtbilr) register [15:0], see page 176 ? gptm timera (gptmtar) register [15:0], see page 183 ? gptm timerb (gptmtbr) register [15:0], see page 184 in the 32-bit modes, the gptm translates a 32-bit write access to gptmtailr into a write access to both gptmtailr and gptmtbilr . the resulting word ordering for such a write operation is: gptmtbilr[15:0]:gptmtailr[15:0] . likewise, a read access to gptmtar returns the value: gptmtbr[15:0]:gptmtar[15:0] . 9.2.2.1 32-bit one-shot/periodic timer mode in 32-bit one-shot and periodic timer modes, th e concatenated versions of the timera and timerb registers are configured as a 32-bit down-counter. the selection of one-shot or periodic mode is determined by the va lue written to the tamr field of the gptm timera mode (gptmtamr) register (see page 166), and there is no need to write to the gptm timerb mode (gptmtbmr) register. when software writes the taen bit in the gptm control (gptmctl) register (see page 168), the timer begins counting down from its preloaded valu e. once the 0x00000000 state is reached, the timer reloads its start value from the concatenated gptmtailr on the next cycle. if configured to be a one-shot timer, the timer stops counting and clears the taen bit in the gptmctl register. if configured as a periodic timer, it continues counting. in addition to reloading the count value, the gptm generates interrupts and output triggers when it reaches the 0x0000000 state. the gptm sets the tatoris bit in the gptm raw interrupt status (gptmris) register (see page 172), and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register (see page 174). if the time -out interrupt is enabled in the gptm interrupt mask (gptimr) register (see page 170), the gptm also sets the tatomis bit in the gptm masked interrupt status (gptmisr) register (see page 173). the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x00000000 state, and deasserted on the following clock cycle. it is enabled by setting the taote bit in gptmctl , and can trigger soc-level events such as adc conversions. if software reloads the gptmtailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tastall bit in the gptmctl register is asserted, the timer freezes counting until the signal is deasserted. 9.2.2.2 32-bit real-time clock timer mode in real-time clock (rtc) mode, the concatenated versions of the timera and timerb registers are configured as a 32-bit up-counter. when rtc mode is selected for the first time, the counter is loaded with a value of 0x00000001. all subseque nt load values must be written to the gptm timera match (gptmtamatchr) register (see page 177) by the controller. the input clock on the ccp0, ccp2 or ccp4 pins is required to be 32.768 khz in rtc mode. the clock signal is then divided down to a 1 hz rate and is passed along to the input of the 32-bit counter.
general-purpose timers 156 may 4, 2007 preliminary when software writes the taen bit in gptmctl , the counter starts counting up from its preloaded value of 0x00000001. when the current count value matches the preloaded value in gptmtamatchr , it rolls over to a value of 0x0000000 0 and continues counting until either a hardware reset, or it is disa bled by software (clearing the taen bit). when a match occurs, the gptm asserts the rtcris bit in gptmris . if the rtc interrupt is enabled in gptimr , the gptm also sets the rtcmis bit in gptmisr and generates a controller interrupt. the status flags are cleared by writing the rtccint bit in gptmicr . if the tastall and/or tbstall bits in the gptmctl register are set, the timer does not freeze if the rtcen bit is set in gptmctl . 9.2.3 16-bit timer operating modes the gptm is placed into global 16-bit mode by writing a value of 0x4 to the gptm configuration (gptmcfg) register (see page 165). this section descr ibes each of the gptm 16-bit modes of operation. timer a and timer b have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-bit one-shot/periodic timer mode in 16-bit one-shot and periodic timer modes, the time r is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. the selection of one-shot or periodic mode is determined by the value written to the tnmr field of the gptmtnmr register. the optional prescaler is loaded into the gptm timern prescale (gptmtnpr) register. when software writes the tnen bit in the gptmctl register, the timer begins counting down from its preloaded value. once the 0x0000 state is r eached, the timer reloads its start value from gptmtnilr and gptmtnpr on the next cycle. if configured to be a one-shot timer, the timer stops counting and clears the tnen bit in the gptmctl register. if configured as a periodic timer, it continues counting. in addition to reloading the coun t value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. the gptm sets the tntoris bit in the gptmris register, and holds it until it is cleare d by writing the gptmicr register. if the time-out interrupt is enabled in gptimr , the gptm also sets the tntomis bit in gptmisr and generates a controller interrupt. the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following cloc k cycle. it is enabled by setting the tnote bit in the gptmctl register, and can trigger soc-level events such as adc conversions. if software reloads the gptmtailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tnstall bit in the gptmctl register is enabled, the timer fr eezes counting until the signal is deasserted. the following example shows a variety of configuratio ns for a 16-bit free running timer while using the prescaler. all values assume a 50-mhz clock with tc=20 ns (clock period).
lm3s817 data sheet may 4, 2007 157 preliminary 9.2.3.2 16-bit input edge count mode in edge count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both . to place the timer in edge count mode, the tncmr bit of the gptmtnmr register must be set to 0. the type of edge that the timer counts is determined by the tnevent fields of the gptmctl register. during initialization, the gptm timern match (gptmtnmatchr) register is configured so that t he difference between the value in the gptmtnilr register and the gptmtnmatchr register equals the number of edge events that must be counted. when software writes the tnen bit in the gptm control (gptmctl) register, the timer is enabled for event capture. each input event on the ccp pin decrements the counter by 1 until the event count matches gptmtnmatchr . when the counts match, the gptm asserts the cnmris bit in the gptmris register (and the cnmmis bit, if the interrupt is not masked). the counter is then reloaded using the value in gptmtnilr , and stopped since the gptm automatically clears the tnen bit in the gptmctl register. once the event count has been reached, all further events are ignored until tnen is re-enabled by software. figure 9-2 shows how input edge count mode works. in this case, the timer start value is set to gptmnilr =0x000a and the match value is set to gptmnmatchr =0x0006 so that four edge events are counted. the counter is configured to detect both edges of the input signal. note that the last two edges are not count ed since the timer automatically clears the tnen bit after the current count matches the value in the gptmnmr register. table 9-1. 16-bit timer with prescaler configurations prescale #clock (t c ) a max time units 00000000 1 1.3107 ms 00000001 2 2.6214 ms 00000010 3 3.9321 ms ------------ -- 11111100 254 332.9229 ms 11111110 255 334. 2336 ms 11111111 256 335. 5443 ms a. t c is the clock period.
general-purpose timers 158 may 4, 2007 preliminary figure 9-2. 16-bit input edge count mode example 9.2.3.3 16-bit input edge time mode in edge time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the gptmtnilr register (or 0xffff at reset). this mode allows for event capture of both rising and falling edges. the timer is placed into edge time mode by setting the tncmr bit in the gptmtnmr register, and the type of event that t he timer captures is determined by the tnevent fields of the gptmctl register. note: prescaler is not available in 16-bit input edge time mode. when software writes the tnen bit in the gptmctl register, the timer is enabled for event capture. when the selected input event is detected, the current tn counter value is captured in the gptmtnr register and is available to be read by the controller. the gptm then asserts the cneris bit (and the cnemis bit, if the interrupt is not masked). after an event has been captured, the timer does no t stop counting. it continues to count until the tnen bit is cleared. when the timer reaches the 0x0000 state, it is reloaded with the value from the gptmnilr register. figure 9-3 shows how input edge timing mode works. in the diagram, it is assumed that the start value of the timer is the default value of 0xffff, an d the timer is configured to capture rising edge events. each time a rising edge event is detected, the current count value is loaded into the gptmtnr register, and is held there until another rising edge is detected (at which point the new count value is loaded into gptmtnr ). 0x000a 0x0006 0x0007 0x0008 0x0009 input signal timer stops, flags asserted timer reload on next cycle ignored ignored count
lm3s817 data sheet may 4, 2007 159 preliminary figure 9-3. 16-bit input edge time mode example 9.2.3.4 16-bit pwm mode the gptm supports a simple pwm generation mode. in pwm mode, the timer is configured as a down-counter with a start value (and thus period) defined by gptmtnilr . pwm mode is enabled with the gptmtnmr register by setting the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. pwm mode can take advantage of the 8-bit prescaler by using the gptm timern prescale register (gptmtnpr) and the gptm timern prescale match register (gptmtnpmr) . this effectively extends the range of the timer to 24 bits. when software writes the tnen bit in the gptmctl register, the counter begins counting down until it reaches the 0x0000 state. on the next count er cycle, the counter reloads its start value from gptmtnilr (and gptmtnpr if using a prescaler) and continues counting until disabled by software clearing the tnen bit in the gptmctl register. no interrupts or status bits are asserted in pwm mode. the output pwm signal asserts when the counter is at the value of the gptmtnilr register (its start state), and is deasserted when the counter value equals the value in the gptm timern match register (gptmnmatchr) . software has the capability of inverting the output pwm signal by setting the tnpwml bit in the gptmctl register. figure 9-4 shows how to generate an output pwm with a 1-ms period and a 66% duty cycle assuming a 50-mhz input clock and tnpwml =0 (duty cycle would be 33% for the tnpwml =1 configuration). for this example, the start value is gptmnirl =0xc350 and the match value is gptmnmr =0x411a. gptmtnr=y input signal time count gptmtnr=x gptmtnr=z z x y 0xffff
general-purpose timers 160 may 4, 2007 preliminary figure 9-4. 16-bit pwm mode example 9.3 initialization and configuration to use the general purpose timers, the periphe ral clock must be enabled by setting the gptm0 , gptm1 , and gptm2 bits in the rcgc1 register. this section shows module initia lization and configuration exampl es for each of the supported timer modes. 9.3.1 32-bit one-shot/periodic timer mode the gptm is configured for 32-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the taen bit in the gptmctl register is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x0. 3. set the tamr field in the gptm timera mode register (gptmtamr) : a. write a value of 0x1 for one-shot mode. b. write a value of 0x2 for periodic mode. 4. load the start value into the gptm timera interval load register (gptmtailr) . 5. if interrupts are required, set the tatoim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. 7. poll the tatoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tatocint bit of the gptm interrupt clear register (gptmicr) . output signal time count gptmtnr=gptmnmr gptmtnr=gptmnmr 0xc350 0x411a tnpwml = 0 tnpwml = 1 tnen set
lm3s817 data sheet may 4, 2007 161 preliminary in one-shot mode, the timer stops counting afte r step 7. to re-enable the timer, repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 9.3.2 32-bit real-tim e clock (rtc) mode to use the rtc mode, the timer must have a 32. 768-khz input signal on its ccp0, ccp2 or ccp4 pins. to enable the rtc feature, follow these steps: 1. ensure the timer is disabled (the taen bit is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x1. 3. write the desired match value to the gptm timera match register (gptmtamatchr) . 4. set/clear the rtcen bit in the gptm control register (gptmctl) as desired. 5. if interrupts are required, set the rtcim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. when the timer count equals the value in the gptmtamatchr register, the counter is re-loaded with 0x00000000 and begins counting. if an interrupt is enabled, it does not have to be cleared. 9.3.3 16-bit one-shot/periodic timer mode a timer is configured for 16-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration register (gptmcfg) with a value of 0x4. 3. set the tnmr field in the gptm timer mode (gptmtnmr) register: a. write a value of 0x1 for one-shot mode. b. write a value of 0x2 for periodic mode. 4. if a prescaler is to be used, write the prescale value to the gptm timern prescale register (gptmtnpr) . 5. load the start value into the gptm timer interval load register (gptmtnilr) . 6. if interrupts are required, set the tntoim bit in the gptm interrupt mask register (gptmimr) . 7. set the tnen bit in the gptm control register (gptmctl) to enable the timer and start counting. 8. poll the tntoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tntocint bit of the gptm interrupt clear register (gptmicr) . in one-shot mode, the timer stops counting afte r step 8. to re-enable the timer, repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 9.3.4 16-bit input edge count mode a timer is configured to input edge count mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x0 and the tnmr field to 0x3.
general-purpose timers 162 may 4, 2007 preliminary 4. configure the type of event(s) that the timer captures by writing the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timern interval load (gptmtnilr) register. 6. load the desired event count into the gptm timern match (gptmtnmatchr) register. 7. if interrupts are required, set the cnmim bit in the gptm interrupt mask (gptmimr) register. 8. set the tnen bit in the gptmctl register to enable the timer and begin waiting for edge events. 9. poll the cnmris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnmcint bit of the gptm interrupt clear (gptmicr) register. in input edge count mode, the timer stops after the desired number of edge events has been detected. to re-enable the timer, ensure that the tnen bit is cleared and repeat steps 4-9. 9.3.5 16-bit input edge timing mode a timer is configured to input edge timing mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm timer mode (gptmtnmr) register, write the tncmr field to 0x1 and the tnmr field to 0x3. 4. configure the type of event that the timer captures by writing the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timern interval load (gptmtnilr) register. 6. if interrupts are required, set the cneim bit in the gptm interrupt mask (gptmimr) register. 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and start counting. 8. poll the cneris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnecint bit of the gptm interrupt clear (gptmicr) register. the time at whic h the event happened can be obtained by reading the gptm timern (gptmtnr) register. in input edge timing mode, the timer continues r unning after an edge event has been detected, but the timer interval can be changed at any time by writing the gptmtnilr register. the change takes effect at the next cycle after the write. 9.3.6 16-bit pwm mode a timer is configured to pwm mode using the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. write the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm timer mode (gptmtnmr) register, set the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. 4. configure the output state of the pwm signal (whether or not it is inverted) in the tnevent field of the gptm control (gptmctl) register. 5. load the timer start value into the gptm timern interval load (gptmtnilr) register. 6. load the gptm timern match (gptmtnmatchr) register with the desired value.
lm3s817 data sheet may 4, 2007 163 preliminary 7. if a prescaler is going to be used, configure the gptm timern prescale (gptmtnpr) register and the gptm timern prescale match (gptmtnpmr) register. 8. set the tnen bit in the gptm control (gptmctl) register to enable the timer and begin generation of the output pwm signal. in pwm timing mode, the timer continues running after the pwm signal has been generated. the pwm period can be adjusted at any time by writing the gptmtnilr register, and the change takes effect at the next cycle after the write. 9.4 register map table 9-1 lists the gptm registers. the offset listed is a hexadecimal increment to the register?s address, relative to that timer?s base address: ? timer0: 0x40030000 ? timer1: 0x40031000 ? timer2: 0x40032000 table 9-2. gptm register map offset name reset type description see page 0x000 gptmcfg 0x00000000 r/w configuration 165 0x004 gptmtamr 0x00000000 r/w timera mode 166 0x008 gptmtbmr 0x00000000 r/w timerb mode 167 0x00c gptmctl 0x00000000 r/w control 168 0x018 gptmimr 0x00000000 r/w interrupt mask 170 0x01c gptmris 0x00000000 ro interrupt status 172 0x020 gptmmis 0x00000000 ro masked interrupt status 173 0x024 gptmicr 0x00000000 w1c interrupt clear 174 0x028 gptmtailr 0x0000ffff a 0xffffffff r/w timera interval load 175 0x02c gptmtbilr 0x0000ffff r/w timerb interval load 176 0x030 gptmtamatchr 0x0000ffff a 0xffffffff r/w timera match 177 0x034 gptmtbmatchr 0x0000ffff r/w timerb match 178 0x038 gptmtapr 0x00000000 r/w timera prescale 179 0x03c gptmtbpr 0x00000000 r/w timerb prescale 180 0x040 gptmtapmr 0x00000000 r/w timera prescale match 181 0x044 gptmtbpmr 0x00000000 r/w timerb prescale match 182
general-purpose timers 164 may 4, 2007 preliminary 9.5 register descriptions the remainder of this section lists and describes the gptm registers, in numerical order by address offset. 0x048 gptmtar 0x0000ffff a 0xffffffff ro timera 183 0x04c gptmtbr 0x0000ffff ro timerb 184 a. the default reset value for the gptmtailr , gptmtamatchr , and gptmtar registers is 0x0000ffff when in 16-bit mode and 0xffffffff when in 32-bit mode. table 9-2. gptm register map (continued) offset name reset type description see page
lm3s817 data sheet may 4, 2007 165 preliminary register 1: gptm configuration (gptmcfg), offset 0x000 this register configures the gl obal operation of the gptm modu le. the value written to this register determines whether the gptm is in 32- or 16-bit mode. bit/field name type reset description 31:3 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 2:0 gptmcfg r/w 0 gptm configuration 0x0: 32-bit timer configuration. 0x1: 32-bit real-time clock (rtc) counter configuration. 0x2: reserved. 0x3: reserved. 0x4-0x7: 16-bit timer configuration, function is controlled by bits 1:0 of gptmtamr and gptmtbmr . reserved ro 0 gptm configuration (gptmcfg) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w reserved gptmcfg
general-purpose timers 166 may 4, 2007 preliminary register 2: gptm timera mode (gptmtamr), offset 0x004 this register configures the gptm bas ed on the configuration selected in the gptmcfg register. when in 16-bit pwm mode, set the taams bit to 0x1, the tacmr bit to 0x0, and the tamr field to 0x2. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 taams r/w 0 gptm timera alternate mode select 0: capture mode is enabled. 1: pwm mode is enabled. note: to enable pwm mode, you must also clear the tacmr bit and set the tamr field to 0x2. 2 tacmr r/w 0 gptm timera capture mode 0: edge-count mode. 1: edge-time mode. 1:0 tamr r/w 0 gptm timera mode 0x0: reserved. 0x1: one-shot timer mode. 0x2: periodic timer mode. 0x3: capture mode. the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register (16-or 32-bit). in 16-bit timer configuration, tamr controls the 16-bit timer modes for timera. in 32-bit timer configuration, th is register controls the mode and the contents of gptmtbmr are ignored. reserved ro 0 gptm timera mode (gptmtamr) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved tamr taams tacmr
lm3s817 data sheet may 4, 2007 167 preliminary register 3: gptm timerb mo de (gptmtbmr), offset 0x008 this register configures the gptm bas ed on the configuration selected in the gptmcfg register. when in 16-bit pwm mode, set the tbams bit to 0x1, the tbcmr bit to 0x0, and the tbmr field to 0x2. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 tbams r/w 0 gptm timerb alternate mode select 0: capture mode is enabled. 1: pwm mode is enabled. note: to enable pwm mode, you must also clear the tbcmr bit and set the tbmr field to 0x2. 2 tbcmr r/w 0 gptm timerb capture mode 0: edge-count mode. 1: edge-time mode. 1:0 tbmr r/w 0 gptm timerb mode 0x0: reserved. 0x1: one-shot timer mode. 0x2: periodic timer mode. 0x3: capture mode. the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register. in 16-bit timer configuration, t hese bits control the 16-bit timer modes for timerb. in 32-bit timer configuration, th is register?s contents are ignored and gptmtamr is used. reserved ro 0 gptm timerb mode (gptmtbmr) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved tbmr tbams tbcmr
general-purpose timers 168 may 4, 2007 preliminary register 4: gptm control (gptmctl), offset 0x00c this register is used alongside the gptmcfg and gmtmtnmr registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. the output trigger can be used to initia te transfers on the adc module. bit/field name type reset description 31:15 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 14 tbpwml r/w 0 gptm timerb pwm output level 0: output is unaffected. 1: output is inverted. 13 tbote r/w 0 gptm timerb output trigger enable 0: the output timerb trigger is disabled. 1: the output timerb trigger is enabled. 12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11:10 tbevent r/w 0 gptm timerb event mode 00: positive edge. 01: negative edge. 10: reserved. 11: both edges. 9 tbstall r/w 0 gptm timerb stall enable 0: timerb stalling is disabled. 1: timerb stalling is enabled. 8 tben r/w 0 gptm timerb enable 0: timerb is disabled. 1: timerb is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. 7 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. res ro 0 gptm control (gptmctl) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 r/w r/w ro r/w r/w r/w r/w ro r/w r/w r/w r/w r/w r/w r/w tbpwml reserved res tbevent res tbote tbstall tben tapwml taevent taote tastall taen rtcen
lm3s817 data sheet may 4, 2007 169 preliminary 6 tapwml r/w 0 gptm timera pwm output level 0: output is unaffected. 1: output is inverted. 5 taote r/w 0 gptm timera output trigger enable 0: the output timera trigger is disabled. 1: the output timera trigger is enabled. 4 rtcen r/w 0 gptm rtc enable 0: rtc counting is disabled. 1: rtc counting is enabled. 3:2 taevent r/w 0 gptm timera event mode 00: positive edge. 01: negative edge. 10: reserved. 11: both edges. 1 tastall r/w 0 gptm timera stall enable 0: timera stalling is disabled. 1: timera stalling is enabled. 0 taen r/w 0 gptm timera enable 0: timera is disabled. 1: timera is enabled and begins counting or the capture logic is enabled based on the gptmcfg register. bit/field name type reset description
general-purpose timers 170 may 4, 2007 preliminary register 5: gptm interrupt mask (gptmimr), offset 0x018 this register allows software to enable/disabl e gptm controller-level interrupts. writing a 1 enables the interrup t, while writing a 0 disables it. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 cbeim r/w 0 gptm captureb event interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 9 cbmim r/w 0 gptm captureb match interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 8 tbtoim r/w 0 gptm timerb time-out interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 rtcim r/w 0 gptm rtc interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 2 caeim r/w 0 gptm capturea event interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. reserved ro 0 gptm interrupt mask (gptmimr) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro r/w r/w r/w ro ro ro ro r/w r/w r/w r/w cbeim reserved cbmim tbtoim reserved rtcim caeim camim tatoim
lm3s817 data sheet may 4, 2007 171 preliminary 1 camim r/w 0 gptm capturea match interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. 0 tatoim r/w 0 gptm timera time-out interrupt mask 0: interrupt is disabled. 1: interrupt is enabled. bit/field name type reset description
general-purpose timers 172 may 4, 2007 preliminary register 6: gptm raw interrupt status (gptmris), offset 0x01c this register shows the state of the gptm's inter nal interrupt signal. these bits are set whether or not the interrupt is masked in the gptmimr register. each bit can be cleared by writing a 1 to its corresponding bit in gptmicr . bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 cberis ro 0 gptm captureb event raw interrupt this is the captureb event interrupt status prior to masking. 9 cbmris ro 0 gptm captureb match raw interrupt this is the captureb match interrupt status prior to masking. 8 tbtoris ro 0 gptm timerb time-out raw interrupt this is the timerb time-out in terrupt status prior to masking. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 rtcris ro 0 gptm rtc raw interrupt this is the rtc event interr upt status prior to masking. 2 caeris ro 0 gptm capturea event raw interrupt this is the capturea event interrupt status prior to masking. 1 camris ro 0 gptm capturea match raw interrupt this is the capturea match interrupt status prior to masking. 0 tatoris ro 0 gptm timera time-out raw interrupt this the timera time-out inte rrupt status prior to masking. reserved ro 0 gptm raw interrupt status (gptmris) offset 0x01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro cberis reserved cbmris tbtoris reserved rtcris caeris camris tatoris
lm3s817 data sheet may 4, 2007 173 preliminary register 7: gptm masked interrupt status (gptmmis), offset 0x020 this register show the state of the gptm's controller-level interrupt. if an interrupt is unmasked in gptmimr , and there is an event that causes the interr upt to be asserted, the corresponding bit is set in this register. all bits are cleared by writing a 1 to the corresponding bit in gptmicr . bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 cbemis ro 0 gptm captureb event masked interrupt this is the captureb event interrupt status after masking. 9 cbmmis ro 0 gptm captureb match masked interrupt this is the captureb match interrupt status after masking. 8 tbtomis ro 0 gptm timerb time-out masked interrupt this is the timerb time-out interrupt status after masking. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 rtcmis ro 0 gptm rtc masked interrupt this is the rtc event interrupt status after masking. 2 caemis ro 0 gptm capturea event masked interrupt this is the capturea event interrupt status after masking. 1 cammis ro 0 gptm capturea match masked interrupt this is the capturea match interrupt status after masking. 0 tatomis ro 0 gptm timera time-out masked interrupt this is the timera time-out interrupt status after masking. reserved ro 0 gptm masked interrupt status (gptmmis) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro cbemis reserved cbmmis tbtomis reserved rtcmis caemis cammis tatomis
general-purpose timers 174 may 4, 2007 preliminary register 8: gptm interrupt clear (gptmicr), offset 0x024 this register is used to clear the status bits in the gptmris and gptmmis registers. writing a 1 to a bit clears the corresponding bit in the gptmris and gptmmis registers. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 cbecint w1c 0 gptm captureb event interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 9 cbmcint w1c 0 gptm captureb match interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 8 tbtocint w1c 0 gptm timerb time-out interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 rtccint w1c 0 gptm rtc interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 2 caecint w1c 0 gptm capturea event interrupt clear 0: the interrupt is unaffected. 1: the interrupt is cleared. 1 camcint w1c 0 gptm capturea match raw interrupt this is the capturea match interrupt status after masking. 0 tatocint w1c 0 gptm timera time-out raw interrupt 0: the interrupt is unaffected. 1: the interrupt is cleared. reserved ro 0 gptm interrupt clear (gptmicr) offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000 00 00000000 ro ro ro w1c w1c w1c w1c ro ro ro ro w1c w1c w1c w1c cbecint rtccint reserved cbmcint tbtocint reserved caecint camcint tatocint
lm3s817 data sheet may 4, 2007 175 preliminary register 9: gptm timera interval load (gptmtailr), offset 0x028 this register is used to load the starting count va lue into the timer. when gptm is configured to one of the 32-bit modes, gptmtailr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm timerb interval load (gptmtbilr) register). in 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of gptmtbilr . bit/field name type reset description 31:16 tailrh r/w 0xffff (32-bit mode) 0x0000 (16-bit mode) gptm timera interval load register high when configured for 32-bit mode via the gptmcfg register, the gptm timerb interval load (gptmtbilr) register loads this value on a write. a read returns the current value of gptmtbilr . in 16-bit mode, this field reads as 0 and does not have an effect on the state of gptmtbilr . 15:0 tailrl r/w 0xffff gptm timera interval load register low for both 16- and 32-bit modes, writing this field loads the counter for timera. a read re turns the current value of gptmtailr . tailrl r/w 1/0 gptm timera interval load (gptmtailr) offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 1 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tailrh 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
general-purpose timers 176 may 4, 2007 preliminary register 10: gptm timerb interval load (gptmtbilr), offset 0x02c this register is used to load the starting count va lue into timerb. when the gptm is configured to a 32-bit mode, gptmtbilr returns the current value of timerb and ignores writes. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 tbilrl r/w 0xffff gptm timerb interval load register when the gptm is not configured as a 32-bit timer, a write to this field updates gptmtbilr . in 32-bit mode, writes are ignored, and reads return the current value of gptmtbilr . tbilrl ro 0 gptm timerb interval load (gptmtbilr) offset 0x02c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 1 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved
lm3s817 data sheet may 4, 2007 177 preliminary register 11: gptm timera match (gptmtamatchr), offset 0x030 this register is used in 32-bit real-time clo ck mode and 16-bit pwm and input edge count modes. bit/field name type reset description 31:16 tamrh r/w 0xffff (32-bit mode) 0x0000 (16-bit mode) gptm timera match register high when configured for 32-bit real-time clock (rtc) mode via the gptmcfg register, this value is compared to the upper half of gptmtar , to determine match events. in 16-bit mode, this field reads as 0 and does not have an effect on the state of gptmtbmatchr . 15:0 tamrl r/w 0xffff gptm timera match register low when configured for 32-bit real-time clock (rtc) mode via the gptmcfg register, this value is compared to the lower half of gptmtar , to determine match events. when configured for pwm mode, this value along with gptmtailr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmtailr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtailr minus this value. r/w offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tamrh gptm timera match (gptmtamatchr) tamrl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w 1 reset type 111111111111111 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode. r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
general-purpose timers 178 may 4, 2007 preliminary register 12: gptm timerb ma tch (gptmtbmatchr), offset 0x034 this register is used in 32-bit real-time clo ck mode and 16-bit pwm and input edge count modes. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 tbmrl r/w 0xffff gptm timerb match register low when configured for pwm mode, this value along with gptmtbilr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmtbilr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtbilr minus this value. tbmrl 15 14 13 12 11 10 9876543210 r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w gptm timerb match (gptmtbmatchr) ro 0 offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved
lm3s817 data sheet may 4, 2007 179 preliminary register 13: gptm timera prescale (gptmtapr), offset 0x038 this register allows software to extend the range of the 16-bit timers. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tapsr r/w 0 gptm timera prescale the register loads this value on a write. a read returns the current value of the register. refer to table 9-1 on page 157 for more details and an example. reserved ro 0 gptm timera prescale (gptmtapr) offset 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tapsr
general-purpose timers 180 may 4, 2007 preliminary register 14: gptm timerb prescale (gptmtbpr), offset 0x03c this register allows software to extend the range of the 16-bit timers. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tbpsr r/w 0 gptm timerb prescale the register loads this value on a write. a read returns the current value of this register. refer to table 9-1 on page 157 for more details and an example. reserved ro 0 gptm timerb prescale (gptmtbpr) offset 0x03c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tbpsr
lm3s817 data sheet may 4, 2007 181 preliminary register 15: gptm timera prescale match (gptmtapmr), offset 0x040 this register effectivel y extends the range of gptmtamatchr to 24 bits. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tapsmr r/w 0 gptm timera prescale match this value is used alongside gptmtamatchr to detect timer match events while using a prescaler. reserved ro 0 gptm timera prescale match (gptmtapmr) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tapsmr
general-purpose timers 182 may 4, 2007 preliminary register 16: gptm timerb prescale match (gptmtbpmr), offset 0x044 this register effectivel y extends the range of gptmtbmatchr to 24 bits. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 tbpsmr r/w 0 gptm timerb prescale match this value is used alongside gptmtbmatchr to detect timer match events while using a prescaler. reserved ro 0 gptm timerb prescale match (gptmtbpmr) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved tbpsmr
lm3s817 data sheet may 4, 2007 183 preliminary register 17: gptm timera (gptmtar), offset 0x048 this register shows the current value of the timera counter in all cases except for input edge count mode. when in this mode, th is register contains the time at which the last edge event took place. bit/field name type reset description 31:16 tarh ro 0xffff (32-bit mode) 0x0000 (16-bit mode) gptm timera register high if the gptmcfg is in a 32-bit mode, timerb value is read. if the gptmcfg is in a 16-bit mode, this is read as zero. 15:0 tarl ro 0xffff gptm timera register low a read returns the current value of the gptm timera count register , except in input edge count mode, when it returns the timestamp from the last edge event. tarl ro 1/0 gptm timera (gptmtar) offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro tarh 1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
general-purpose timers 184 may 4, 2007 preliminary register 18: gptm timerb (gptmtbr), offset 0x04c this register shows the current value of the timerb counter in all cases except for input edge count mode. when in this mode, th is register contains the time at which the last edge event took place. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 tbrl ro 0xffff gptm timerb a read returns the current value of the gptm timerb count register , except in input edge count mode, when it returns the timestamp from the last edge event. tbrl ro 0 gptm timerb (gptmtbr) offset 0x04c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved
lm3s817 data sheet may 4, 2007 185 preliminary 10 watchdog timer a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain co ntrol when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. the stellaris watchdog timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a lo cking register, and user-enabled stalling. the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the watchdog timer has been configured, the lock register can be writte n to prevent the timer configuration from being inadvertently altered. 10.1 block diagram figure 10-1. wdt module block diagram control / clock / interrupt generation wdtctl wdticr wdtris wdtmis wdtlock wdttest wdtload wdtvalue comparator 32-bit down counter 0x00000000 interrupt system clock identification registers wdtpcellid0 wdtperiphid0 wdtperiphid4 wdtpcellid1 wdtperiphid1 wdtperiphid5 wdtpcellid2 wdtperiphid2 wdtperiphid6 wdtpcellid3 wdtperiphid3 wdtperiphid7
watchdog timer 186 may 4, 2007 preliminary 10.2 functional description the watchdog timer module consists of a 32-bi t down counter, a programmable load register, interrupt generation logic, and a locking register . once the watchdog timer has been configured, the watchdog timer lock (wdtlock) register is written, which pr events the timer configuration from being inadvertently altered by software. the watchdog timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the co unter also enables the watchdog timer interrupt. after the first time-out event, the 32-bit counter is re-loaded with the value of the watchdog timer load (wdtload) register, and the timer resumes counting down from that value. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the watchdogresetenable function), the watchdog timer asserts its reset signal to the system. if the interr upt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the wdtload register, and counting resumes from that value. if wdtload is written with a new value while the watc hdog timer counter is counting, then the counter is loaded with the new value and continues counting. writing to wdtload does not clear an active interrupt. an interrupt must be specifically cleared by writing to the watchdog interrupt clear (wdticr) register. the watchdog module interrupt and reset generation can be enabled or disabled as required. when the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 initialization and configuration to use the wdt, its peripheral clock must be enabled by setting the wdt bit in the rcgc0 register. the watchdog timer is configured using the following sequence: 1. load the wdtload register with the desired timer load value. 2. if the watchdog is configured to trigger system resets, set the resen bit in the wdtctl register. 3. set the inten bit in the wdtctl register to enable the watchdog and lock the control register. if software requires that all of the watchdog re gisters are locked, the watchdog timer module can be fully locked by writing any value to the wdtlock register. to unlock the watchdog timer, write a value of 0x1acce551. 10.4 register map table 10-1 lists the watchdog registers. the offset listed is a hexadecimal increment to the register?s address, relative to the watchdog timer base address of 0x40000000. table 10-1. wdt register map offset name reset type description see page 0x000 wdtload 0xffffffff r/w load 188 0x004 wdtvalue 0xffffffff ro current value 189 0x008 wdtctl 0x00000000 r/w control 190
lm3s817 data sheet may 4, 2007 187 preliminary 10.5 register descriptions the remainder of this section lists and describes the wdt registers, in numerical order by address offset. 0x00c wdticr - wo interrupt clear 191 0x010 wdtris 0x00000000 ro raw interrupt status 192 0x014 wdtmis 0x00000000 ro masked interrupt status 193 0x418 wdttest 0x00000000 r/w watchdog stall enable 195 0xc00 wdtlock 0x00000000 r/w lock 194 0xfd0 wdtperiphid4 0x00000000 ro peripheral identification 4 196 0xfd4 wdtperiphid5 0x00000000 ro peripheral identification 5 197 0xfd8 wdtperiphid6 0x00000000 ro peripheral identification 6 198 0xfdc wdtperiphid7 0x00000000 ro peripheral identification 7 199 0xfe0 wdtperiphid0 0x00000005 ro peripheral identification 0 200 0xfe4 wdtperiphid1 0x00000018 ro peripheral identification 1 201 0xfe8 wdtperiphid2 0x00000018 ro peripheral identification 2 202 0xfec wdtperiphid3 0x00000001 ro peripheral identification 3 203 0xff0 wdtpcellid0 0x0000000d ro primecell identification 0 204 0xff4 wdtpcellid1 0x000000f0 ro primecell identification 1 205 0xff8 wdtpcellid2 0x00000005 ro primecell identification 2 206 0xffc wdtpcellid3 0x000000b1 ro primecell identification 3 207 table 10-1. wdt register map (continued) offset name reset type description see page
watchdog timer 188 may 4, 2007 preliminary register 1: watchdog load (wdtload), offset 0x000 this register is the 32-bit interval value used by th e 32-bit counter. when this register is written, the value is immediately loaded and the counter restarts counting down from the new value. if the wdtload register is loaded with 0x00000000, an interrupt is immediately generated. bit/field name type reset description 31:0 wdtload r/w 0xffffffff watchdog load value wdtload r/w 1 watchdog load (wdtload) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 1 reset type 111111111111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w wdtload
lm3s817 data sheet may 4, 2007 189 preliminary register 2: watchdog value (wdtvalue), offset 0x004 this register contains the current count value of the timer. bit/field name type reset description 31:0 wdtvalue ro 0xffffffff watchdog value current value of the 32-bit down counter. wdtvalue ro 1 watchdog value (wdtvalue) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1 reset type 111111111111111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro wdtvalue
watchdog timer 190 may 4, 2007 preliminary register 3: watchdog control (wdtctl), offset 0x008 this register is the watchdog control register. the watchdog timer can be configured to generate a reset signal (upon second time-out) or an interrupt on time-out. when the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. the only mechanism that can re -enable writes is a hardware reset. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 resen r/w 0 watchdog reset enable 0: disabled. 1: enable the watchdog module reset output. 0 inten r/w 0 watchdog interrupt enable 0: interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset) 1: interrupt event enabled. once enabled, all writes are ignored. reserved ro 0 watchdog control (wdtctl) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w inten reserved resen
lm3s817 data sheet may 4, 2007 191 preliminary register 4: watchdog interrupt clear (wdticr), offset 0x00c this register is the interrupt clear register. a write of any value to this register clears the watchdog interrupt and reloads the 32-bit counter from the wdtload register. value for a read or reset is indeterminate. bit/field name type reset description 31:0 wdtintclr wo - watchdog interrupt clear wdtintclr wo - watchdog interrupt clear (wdticr) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type --------------- wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo - reset type --------------- wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wdtintclr
watchdog timer 192 may 4, 2007 preliminary register 5: watchdog raw interrupt status (wdtris), offset 0x010 this register is the raw interrupt status register. watchdog interrupt events can be monitored via this register if the cont roller interrupt is masked. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 wdtris ro 0 watchdog raw interrupt status gives the raw interrupt state (prior to masking) of wdtintr . reserved ro 0 watchdog raw interrupt status (wdtris) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro wdtris reserved
lm3s817 data sheet may 4, 2007 193 preliminary register 6: watchdog masked interrupt status (wdtmis), offset 0x014 this register is the masked interrupt status register. the value of this register is the logical and of the raw interrupt bit and the watchdog interrupt enable bit. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 wdtmis ro 0 watchdog masked interrupt status gives the masked interrupt state (after masking) of the wdtintr interrupt. reserved ro 0 watchdog masked interrupt status (wdtmis) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro wdtmis reserved
watchdog timer 194 may 4, 2007 preliminary register 7: watchdog lock (wdtlock), offset 0xc00 writing 0x1acce551 to the wdtlock register enables write access to all other registers. writing any other value to the wdtlock register re-enables the locked state for register writes to all the other registers. reading the wdtlock register returns the lock status rather than the 32-bit value written. therefore, when writ e accesses are disabled, reading the wdtlock register returns 0x00000001 (when locked; otherwise, the returned value is 0x00000000 (unlocked)). bit/field name type reset description 31:0 wdtlock r/w 0x0000 watchdog lock a write of the value 0x1acce551 unlocks the watchdog registers for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: locked: 0x00000001 unlocked: 0x00000000 wdtlock r/w 0 watchdog lock (wdtlock) offset 0xc00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w wdtlock
lm3s817 data sheet may 4, 2007 195 preliminary register 8: watchdog test (wdttest), offset 0x418 this register provides user-enabled stalling when the microcontroller a sserts the cpu halt flag during debug. bit/field name type reset description 31:9 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 8 stall r/w 0 watchdog stall enable when set to 1, if the stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. once the microcontroller is rest arted, the watchdog timer resumes counting. 7:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. ro 0 watchdog test (wdttest) offset 0x418 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro r/w ro ro ro ro ro ro ro ro stall reserved reserved reserved
watchdog timer 196 may 4, 2007 preliminary register 9: watchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 wdt peripheral id register[7:0] reserved ro 0 watchdog peripheral identification 4 (wdtperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
lm3s817 data sheet may 4, 2007 197 preliminary register 10: watchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 wdt peripheral id register[15:8] reserved ro 0 watchdog peripheral identification 5 (wdtperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
watchdog timer 198 may 4, 2007 preliminary register 11: watchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 wdt peripheral id register[23:16] reserved ro 0 watchdog peripheral identification 6 (wdtperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
lm3s817 data sheet may 4, 2007 199 preliminary register 12: watchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 wdt peripheral id register[31:24] reserved ro 0 watchdog peripheral identification 7 (wdtperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
watchdog timer 200 may 4, 2007 preliminary register 13: watchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x05 watchdog peripheral id register[7:0] reserved ro 0 watchdog peripheral identification 0 (wdtperiphid0) offset 0xfe0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
lm3s817 data sheet may 4, 2007 201 preliminary register 14: watchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x18 watchdog peripheral id register[15:8] reserved ro 0 watchdog peripheral identification 1 (wdtperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
watchdog timer 202 may 4, 2007 preliminary register 15: watchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 watchdog peripheral id register[23:16] reserved ro 0 watchdog peripheral identification 2 (wdtperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
lm3s817 data sheet may 4, 2007 203 preliminary register 16: watchdog peripheral identification 3 (wdtperiphid3), offset 0xfec the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x01 watchdog peripheral id register[31:24] reserved ro 0 watchdog peripheral identification 3 (wdtperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
watchdog timer 204 may 4, 2007 preliminary register 17: watchdog primecell identi fication 0 (wdtpcellid0), offset 0xff0 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d watchdog primecell id register[7:0] reserved ro 0 watchdog primecell identification 0 (wdtpcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
lm3s817 data sheet may 4, 2007 205 preliminary register 18: watchdog primecell identi fication 1 (wdtpcellid1), offset 0xff4 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 watchdog primecell id register[15:8] reserved ro 0 watchdog primecell identification 1 (wdtpcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
watchdog timer 206 may 4, 2007 preliminary register 19: watchdog primecell identi fication 2 (wdtpcellid2), offset 0xff8 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 watchdog primecell id register[23:16] reserved ro 0 watchdog primecell identification 2 (wdtpcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
lm3s817 data sheet may 4, 2007 207 preliminary register 20: watchdog primecell identifi cation 3 (wdtpcellid3 ), offset 0xffc the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 watchdog primecell id register[31:24] reserved ro 0 watchdog primecell identification 3 (wdtpcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
analog-to-digital converter (adc) 208 may 4, 2007 preliminary 11 analog-to-digital converter (adc) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number. the stellaris adc module features 10-bit conversi on resolution and supports six input channels, plus an internal temperature sensor. the adc module contains a programmable sequencer which allows for the sampling of multip le analog input sources without controller intervention. each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. the stellaris adc provides the following features: ? six analog input channels ? single-ended and differential-input configurations ? internal temperature sensor ? sample rate of one million samples/second ? four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result fifos ? flexible trigger control ? controller (software) ? timers ? analog comparator ? pwm ? gpio ? hardware averaging of up to 64 samples for improved accuracy
lm3s817 data sheet may 4, 2007 209 preliminary 11.1 block diagram figure 11-1. adc module block diagram 11.2 functional description the stellaris adc collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approach found on many adc modules. each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the adc to collect data from mult iple input sources without having to be re-configured or serviced by the controller. the programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. 11.2.1 sample sequencers the sampling control and data capture is hand led by the sample sequencers. all of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the fifo. table 11-1 shows the maximum number of samples that each sequencer can capture and its corresponding fifo de pth. in this implementation, each fifo entry is a 32-bit word, with the lower 10 bits containing the conversion result. table 11-1. samples and fifo depth of sequencers sequencer number of samples depth of fifo ss3 1 1 ss2 4 4 ss1 4 4 ss0 8 8 analog-to-digital converter adcssfstat0 adcssctl0 adcssmux0 sample sequencer 0 adcssfstat1 adcssctl1 adcssmux1 sample sequencer 1 adcssfstat2 adcssctl2 adcssmux2 sample sequencer 2 adcssfstat3 adcssctl3 adcssmux3 sample sequencer 3 adcustat adcostat adcactss control/status adcsspri adcisc adcris adcim interrupt control adcemux adcpssi ss0 interrupt trigger events ss1 interrupt ss2 interrupt ss3 interrupt ss0 ss1 ss2 ss3 comparator gpio (pb4) timer pwm comparator gpio (pb4) timer pwm comparator gpio (pb4) timer pwm comparator gpio (pb4) timer pwm adcssfifo0 adcssfifo1 adcssfifo2 adcssfifo3 fifo block hardware averager adcsac
analog-to-digital converter (adc) 210 may 4, 2007 preliminary for a given sample sequence, each sample is defined by two 4-bit nibbles in the adc sample sequence input multiplexer select (adcssmuxn) and adc sample seque nce control (adcssctln) registers, where "n" corresponds to the sequence number. the adcssmuxn nibbles select the input pin, while the adcssctln nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. sample sequencers are enabled by setting the respective asenn bit in the adc active sample sequencer (adcactss) register, but can be configured before being enabled. when configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. in the adcssctln register, the interrupt enable (ie) bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. also, the end bit can be set at any point within a sample sequence. for example, if sequencer 0 is used, the end bit can be set in the nibble associated with the fifth sample, allowing sequencer 0 to complete exec ution of the sample s equence after the fifth sample. after a sample sequence completes execution, the result data can be retrieved from the adc sample sequence result fifo (adcssfifon) registers. the fifos are simple circular buffers that read a single address to "pop" result data. for software debug purposes, the positions of the fifo head and tail pointers are visible in the adc sample sequence fifo status (adcssfstatn) registers along with full and empty status flags. overflow and underflow conditions are monitored using the adcostat and adcustat registers. 11.2.2 module control outside of the sample sequencers, the remainder of the control logic is re sponsible for tasks such as interrupt generation, sequence prioritization, and trigger configuration. most of the adc control logic runs at the adc clo ck rate of 14-18 mhz. the internal adc divider is configured automatically by hardware when the system xtal is selected. the automatic clock divider configuration targets 16.667 mhz operation for all stellaris devices. 11.2.2.1 interrupts the sample sequencers dictate the events that ca use interrupts, but they don't have control over whether the interrupt is actually sent to the interrupt controller. the adc module's interrupt signal is controlled by the state of the mask bits in the adc interrupt mask (adcim) register. interrupt status can be viewed at two locations: the adc raw interrupt status (adcris) register, which shows the raw status of a sample sequencer's interrupt signal, and the adc interrupt status and clear (adcisc) register, which shows the logical and of the adcris register?s inr bit and the adcim register?s mask bits. interrupts are cleared by writing a 1 to the corresponding in bit in adcisc . 11.2.2.2 prioritization when sampling events (triggers) happen concurrent ly, they are prioritized for processing by the values in the adc sample sequencer priority (adcsspri) register. valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. multiple active sample sequencer units with the same priority do not provid e consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 11.2.2.3 sampling events sample triggering for each sample sequencer is defined in the adc event multiplexer select (adcemux) register. the external peripheral triggerin g sources vary by stellaris family member, but all devices share the "controller" and "alway s" triggers. software can initiate sampling by setting the ch bits in the adc processor sample sequ ence initiate (adcpssi) register.
lm3s817 data sheet may 4, 2007 211 preliminary when using the "always" trigger, care must be tak en. if a sequence's priority is too high, it is possible to starve other lower priority sequences. 11.2.3 hardware sample averaging circuit higher precision results can be generated using th e hardware averaging circuit, however, the improved results are at the cost of throughput. up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer fifo. throughput is decreased proportionally to the number of samples in the av eraging calculation. for example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. by default the averaging circuit is off and all data from the converter passes through to the sequencer fifo. the averaging hardware is co ntrolled by the adc sample averaging control (adcsac) register (see page 223). there is a single averaging circuit and all input channels receive the same amount of averaging whethe r they are single-ended or differential. 11.2.4 analog-to-digital converter the converter itself generates a 10-bit output value for selected analog input. special analog pads are used to minimize the distortion on the input. 11.2.5 test modes there is a user-available test mode that allows for loopback operation within the digital portion of the adc module. this can be useful for debugging software without having to provide actual analog stimulus. this mode is available through the adc test mode loopback (adctmlb) register (see page 236). 11.2.6 internal temperature sensor the internal temperature sensor provides an an alog temperature reading as well as a reference voltage. the voltage at the output terminal senso is given by the following equation: senso = 2.7 - ((t + 55) / 75) this relation is shown in figure 11-2 on page 211. figure 11-2. internal temperature sensor characteristic 11.3 initialization and configuration in order for the adc module to be used, the pll must be enabled and using a supported crystal frequency (see the rcc register on page 84). using unsupp orted frequencies can cause faulty operation in the adc module.
analog-to-digital converter (adc) 212 may 4, 2007 preliminary 11.3.1 module initialization initialization of the adc module is a simple proc ess with very few steps. the main steps include enabling the clock to the adc and reconfiguring the sample sequencer priorities (if needed). the initialization sequence fo r the adc is as follows: 1. enable the adc clock by writing a value of 0x00010000 to the rcgc1 register in the system control module. 2. if required by the application, reconfigur e the sample sequencer priorities in the adcsspri register. the default configuration has sample sequencer 0 with the highest priority, and sample sequencer 3 as the lowest priority. 11.3.2 sample sequencer configuration configuration of the samp le sequencers is slightly more co mplex than the module initialization since each sample sequence is completely programmable. the configuration for each sample sequencer should be as follows: 1. ensure that the sample sequencer is disa bled by writing a 0 to the corresponding asen bit in the adcactss register. programming of the sample sequencers is allowed without having them enabled. disabling the sequencer during pr ogramming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. configure the trigger event for the sample sequencer in the adcemux register. 3. for each sample in the sample sequence, configure the corresponding input source in the adcssmuxn register. 4. for each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the adcssctln register. when programming the last nibble, ensure that the end bit is set. failu re to set the end bit causes unpredictable behavior. 5. if interrupts are to be used, write a 1 to the corresponding mask bit in the adcim register. 6. enable the sample sequencer logic by writing a 1 to the corresponding asen bit in the adcactss register. 11.4 register map table 11-2 lists the adc registers. the offset liste d is a hexadecimal increment to the register?s address, relative to the adc base address of 0x40038000. table 11-2. adc register map offset name reset type description see page 0x000 adcactss 0x00000000 r/w active sample sequencer 214 0x004 adcris 0x00000000 ro raw interrupt status and clear 215 0x008 adcim 0x00000000 r/ w interrupt mask 216 0x00c adcisc 0x00000000 r/w1c inte rrupt status and clear 217 0x010 adcostat 0x00000000 r/w1c overflow status 218 0x014 adcemux 0x00000000 r/w event multiplexer select 219 0x018 adcustat 0x00000000 r/w1c underflow status 220
lm3s817 data sheet may 4, 2007 213 preliminary 11.5 register descriptions the remainder of this section lists and describes the adc registers, in numerical order by address offset. 0x020 adcsspri 0x00003210 r/w sample sequencer priority 221 0x028 adcpssi - wo processor samp le sequence initiate 222 0x030 adcsac 0x00000000 r/w sample averaging control 223 0x040 adcssmux0 0x00000000 r/w sample sequence input multiplexer select 0 224 0x044 adcssctl0 0x00000000 r/w sample sequence control 0 226 0x048 adcssfifo0 0x00000000 ro sample sequence result fifo 0 228 0x04c adcssfstat0 0x00000100 ro sample sequence fifo 0 status 229 0x060 adcssmux1 0x00000000 r/w sample sequence input multiplexer select 1 230 0x064 adcssctl1 0x00000000 r/w sample sequence control 1 231 0x068 adcssfifo1 0x00000000 ro sample sequence result fifo 1 231 0x06c adcssfstat1 0x00000100 ro sample sequence fifo 1 status 231 0x080 adcssmux2 0x00000000 r/w sample sequence input multiplexer select 2 232 0x084 adcssctl2 0x00000000 r/w sample sequence control 2 233 0x088 adcssfifo2 0x00000000 ro sample sequence result fifo 2 233 0x08c adcssfstat2 0x00000100 ro sample sequence fifo 2 status 233 0x0a0 adcssmux3 0x00000000 r/w sample sequence input multiplexer select 3 234 0x0a4 adcssctl3 0x00000002 r/w sample sequence control 3 235 0x0a8 adcssfifo3 0x00000000 ro sample sequence result fifo 3 235 0x0ac adcssfstat3 0x00000100 ro sample sequence fifo 3 status 235 0x100 adctmlb 0x00000000 r/w test mode loopback 236 table 11-2. adc register map (continued) offset name reset type description see page
analog-to-digital converter (adc) 214 may 4, 2007 preliminary register 1: adc active sample sequencer (adcactss), offset 0x000 this register controls the activation of the sa mple sequencers. each sample sequencer can be enabled/disabled independently. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 asen3 r/w 0 specifies whether sample sequencer 3 is enabled. if set, the sample sequence logic for sequencer 3 is active. otherwise, the sequencer is inactive. 2 asen2 r/w 0 specifies whether sample sequencer 2 is enabled. if set, the sample sequence logic for sequencer 2 is active. otherwise, the sequencer is inactive. 1 asen1 r/w 0 specifies whether sample sequencer 1 is enabled. if set, the sample sequence logic for sequencer 1 is active. otherwise, the sequencer is inactive. 0 asen0 r/w 0 specifies whether sample sequencer 0 is enabled. if set, the sample sequence logic for sequencer 0 is active. otherwise, the sequencer is inactive. reserved asen0 ro 0 adc active sample sequencer (adcactss) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w asen1 asen2 asen3 reserved
lm3s817 data sheet may 4, 2007 215 preliminary register 2: adc raw interrupt status (adcris), offset 0x004 this register shows the status of the raw interr upt signal of each sample sequencer. these bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 inr3 ro 0 set by hardware when a sample with its respective adcssctl3 ie bit has completed conv ersion. this bit is cleared by writing a 1 to the adcisc in3 bit. 2 inr2 ro 0 set by hardware when a sample with its respective adcssctl2 ie bit has completed conv ersion. this bit is cleared by writing a 1 to the adcisc in2 bit. 1 inr1 ro 0 set by hardware when a sample with its respective adcssctl1 ie bit has completed conv ersion. this bit is cleared by writing a 1 to the adcisc in1 bit. 0 inr0 ro 0 set by hardware when a sample with its respective adcssctl0 ie bit has completed conv ersion. this bit is cleared by writing a 1 to the adcisc in0 bit. reserved inr0 ro 0 adc raw interrupt status (adcris) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro inr1 inr2 inr3 reserved
analog-to-digital converter (adc) 216 may 4, 2007 preliminary register 3: adc interrupt mask (adcim), offset 0x008 this register controls whether the sample se quencer raw interrupt signals are promoted to controller interrupts. the raw interrupt signal for each sample sequencer can be masked independently. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 mask3 r/w 0 specifies whether the raw interrupt signal from sample sequencer 3 ( adcris register inr3 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 2 mask2 r/w 0 specifies whether the raw interrupt signal from sample sequencer 2 ( adcris register inr2 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 1 mask1 r/w 0 specifies whether the raw interrupt signal from sample sequencer 1 ( adcris register inr1 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 0 mask0 r/w 0 specifies whether the raw interrupt signal from sample sequencer 0 ( adcris register inr0 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. reserved mask0 ro 0 adc interrupt mask (adcim) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w mask1 mask2 mask3 reserved
lm3s817 data sheet may 4, 2007 217 preliminary register 4: adc interrupt status and clear (adcisc), offset 0x00c this register provides the mechanism for clearing interrupt conditions, and shows the status of controller interrupts generated by the sample sequencers. when read, each bit field is the logical and of the respective inr and mask bits. interrupts are cleared by writing a 1 to the corresponding bit po sition. if software is polling the adcris instead of generating interrupts, the inr bits are still cleared via the adcisc register, even if the in bit is not set. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 in3 r/w1c 0 this bit is set by hardware when the mask3 and inr3 bits are both 1, providing a level-based interrupt to the controller. it is cleared by writing a 1, and also clears the inr3 bit. 2 in2 r/w1c 0 this bit is set by hardware when the mask2 and inr2 bits are both 1, providing a level based interrupt to the controller. it is cleared by writing a 1, and also clears the inr2 bit. 1 in1 r/w1c 0 this bit is set by hardware when the mask1 and inr1 bits are both 1, providing a level based interrupt to the controller. it is cleared by writing a 1, and also clears the inr1 bit. 0 in0 r/w1c 0 this bit is set by hardware when the mask0 and inr0 bits are both 1, providing a level based interrupt to the controller. it is cleared by writing a 1, and also clears the inr0 bit. reserved in0 ro 0 adc interrupt status and clear (adcisc) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c r/w1c r/w1c in1 in2 in3 reserved
analog-to-digital converter (adc) 218 may 4, 2007 preliminary register 5: adc overflow status (adcostat), offset 0x010 this register indicates overflow conditions in the sample sequencer fifos. once the overflow condition has been handled by software, the co ndition can be cleared by writing a 1 to the corresponding bit position. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 ov3 r/w1c 0 this bit specifies that t he fifo for sample sequencer 3 has hit an overflow condition where the fifo is full and a write was requested. when an overfl ow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 2 ov2 r/w1c 0 this bit specifies that t he fifo for sample sequencer 2 has hit an overflow condition where the fifo is full and a write was requested. when an overfl ow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 1 ov1 r/w1c 0 this bit specifies that t he fifo for sample sequencer 1 has hit an overflow condition where the fifo is full and a write was requested. when an overfl ow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 0 ov0 r/w1c 0 this bit specifies that t he fifo for sample sequencer 0 has hit an overflow condition where the fifo is full and a write was requested. when an overfl ow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. reserved ov0 ro 0 adc overflow status (adcostat) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c r/w1c r/w1c ov1 ov2 ov3 reserved
lm3s817 data sheet may 4, 2007 219 preliminary register 6: adc event multiplexer select ( adcemux), offset 0x014 the adcemux selects the event (trigger) that initia tes sampling for each sample sequencer. each sample sequencer can be configured with a unique trigger source. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:12 em3 r/w 0 this field selects the trigger source for sample sequencer 3. the valid configurations for this field are: 11:8 em2 r/w 0 this field selects the trigger source for sample sequencer 2. the encodings are the same as those for em3. 7:4 em1 r/w 0 this field selects the trigger source for sample sequencer 1. the encodings are the same as those for em3. 3:0 em0 r/w 0 this field selects the trigger source for sample sequencer 0. the encodings are the same as those for em3. em0 ro 0 adc event multiplexer select (adcemux) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved em1 em2 em3 em binary value event 0000 controller (default) 0001 analog comparator 0 0010 reserved 0011 reserved 0100 external (gpio pb4) 0101 timer 0110 pwm0 0111 pwm1 1000 pwm2 1001-1110 reserved 1111 always (continuously sample)
analog-to-digital converter (adc) 220 may 4, 2007 preliminary register 7: adc underflow stat us (adcustat), offset 0x018 this register indicates underflow conditions in the sample sequencer fifos. the corresponding underflow condition can be cleared by wr iting a 1 to the relevant bit position. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 uv3 r/w1c 0 this bit specifies that the fifo for sample sequencer 3 has hit an underflow condition where the fifo is empty and a read was requested. the probl ematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 2 uv2 r/w1c 0 this bit specifies that t he fifo for sample sequencer 2 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 1 uv1 r/w1c 0 this bit specifies that t he fifo for sample sequencer 1 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 0 uv0 r/w1c 0 this bit specifies that t he fifo for sample sequencer 0 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. reserved uv0 ro 0 adc underflow status (adcustat) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w1c r/w1c r/w1c r/w1c uv1 uv2 uv3 reserved
lm3s817 data sheet may 4, 2007 221 preliminary register 8: adc sample sequencer priority (a dcsspri), offset 0x020 this register sets the priority for each of the sample sequencers. out of reset, sequencer 0 has the highest priority, and sample sequence 3 has the lowest priority. when reconfiguring sequence priorities, each sequence must have a unique pr iority or the adc behavior is inconsistent. bit/field name type reset description 31:14 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 13:12 ss3 r/w 0x3 the ss3 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 3. a priority encoding of 0 is highest and 3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. adc behavior is not consistent if two or more fields are equal. 11:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9:8 ss2 r/w 0x2 the ss2 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 2. 7:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:4 ss1 r/w 0x1 the ss1 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 1. 3:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1:0 ss0 r/w 0x0 the ss0 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 0. reserved reserved reserved reserved ro 0 adc sample sequencer priority (adcsspri) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 011001000010000 ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w reserved ss0 ss1 ss2 ss3
analog-to-digital converter (adc) 222 may 4, 2007 preliminary register 9: adc processo r sample sequence initiate (adcpssi), offset 0x028 this register provides a mechanism for applicatio n software to initiate sampling in the sample sequencers. sample sequen ces can be initiated individually or in any combination. when multiple sequences are triggered simultaneously, the priority encodings in adcsspri dictate execution order. bit/field name type reset description 31:4 reserved wo - only a write by software is valid; a read of the register returns no meaningful data. 3 ss3 wo - only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 3, assuming the sequencer is enabled in the adcactss register. 2 ss2 wo - only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 2, assuming the sequencer is enabled in the adcactss register. 1 ss1 wo - only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 1, assuming the sequencer is enabled in the adcactss register. 0 ss0 wo - only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 0, assuming the sequencer is enabled in the adcactss register. reserved wo - adc processor sample sequence initiate (adcpssi) offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type --------------- wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo - reset type --------------- wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reserved ss0 ss1 ss2 ss3
lm3s817 data sheet may 4, 2007 223 preliminary register 10: adc sample averagin g control (adcsac) , offset 0x030 this register controls the amount of hardware averaging applied to conversion results. the final conversion result stored in the fifo is averaged from 2 avg consecutive adc samples at the specified adc speed. if avg is 0, the sample is pa ssed directly through without any averaging. if avg is 6, 64 consecutive adc samples are aver aged to generate one result in the sequencer fifo. an avg = 7 provides unpredictable results. bit/field name type reset description 31:3 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 2:0 avg r/w 0 specifies the amount of hardware averaging that will be applied to adc samples. the avg field can be any value between 0 and 6. entering a value of 7 creates unpredictable results. reserved ro 0 adc sample averaging control (adcsac) offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w reserved avg
analog-to-digital converter (adc) 224 may 4, 2007 preliminary register 11: adc sample seque nce input multiplexer select 0 (adcssmux0), offset 0x040 this register defines the analog input configurat ion for each sample in a sequence executed with sample sequencer 0. this register is 32-bits wide and contains information for eight possible samples. bit/field name type reset description 31:30 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 29:28 mux7 r/w 0 the mux7 field is used during the eighth sample of a sequence executed with sample sequencer 0. it specifies which of the analog inputs is sampled for the analog-to-digital conversion. the value set here indicates the corresponding pin, for example, a value of 1 indicates the input is adc1 . 27:26 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 25:24 mux6 r/w 0 the mux6 field is used during the seventh sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 23:22 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 21:20 mux5 r/w 0 the mux5 field is used during the sixth sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 19:18 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 17:16 mux4 r/w 0 the mux4 field is used during the fifth sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15:14 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 13:12 mux3 r/w 0 the mux3 field is used during the fourth sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. ro 0 adc sample sequence input multiplexer select 0 (adcssmux0) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w ro 0 reset type 000000000000000 r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w mux7 mux6 mux5 mux4 mux3 mux2 mux1 mux0 reserved reserved reserved reserved reserved reserved reserved reserved
lm3s817 data sheet may 4, 2007 225 preliminary 11:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9:8 mux2 r/w 0 the mux2 field is used during the third sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 7:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:4 mux1 r/w 0 the mux1 field is used during the second sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 3:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1:0 mux0 r/w 0 the mux0 field is used during the first sample of a sequence executed with sample sequencer 0 and specifies which of the analog inputs is sampled for the analog-to-digital conversion. bit/field name type reset description
analog-to-digital converter (adc) 226 may 4, 2007 preliminary register 12: adc sample sequence control 0 (adcssctl0), offset 0x044 this register contains the configuration information for each sample for a sequence executed with sample sequencer 0. when configuring a sample sequence, the end bit must be set at some point, whether it be after the first sample , last sample, or any sample in between. this register is 32-bits wide and contains information for eight possible samples. bit/field name type reset description 31 ts7 r/w 0 the ts7 bit is used during the eighth sample of the sample sequence and specifies the input source of the sample. if set, the temperature sensor is r ead. otherwise, the input pin specified by the adcssmux register is read. 30 ie7 r/w 0 the ie7 bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal ( inr0 bit) is asserted at the end of the sample's conversion. if the mask0 bit in the adcim register is set, the interrupt is promoted to a controller-level inte rrupt. when this bit is set, the raw interrupt is asserted, otherwise it is not. it is legal to have multiple samples within a sequence generate interrupts. 29 end7 r/w 0 the end7 bit indicates that this is the last sample of the sequence. it is possible to end the sequence on any sample position. samples defined after the sample containing a set end are not requested for conver sion even though the fields may be non-zero. it is required that software write the end bit somewhere within the sequence. (sample sequencer 3, which only has a single sample in the sequence, is hardwired to have the end0 bit set.) setting this bit indicates that th is sample is the last in the sequence. 28 d7 r/w 0 the d7 bit indicates that the analog input is to be differentially sampled. the corresponding adcssmuxx nibble must be set to the pair number "i", where t he paired inputs are "2i and 2i+1". the temperature sensor does not have a differential option. when set, the analog inputs are differentially sampled. 27 ts6 r/w 0 same definition as ts7 but used during the seventh sample. 26 ie6 r/w 0 same definition as ie7 but used during the seventh sample. 25 end6 r/w 0 same definition as end7 but used during the seventh sample. r/w 0 adc sample sequence control 0 (adcssctl0) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ts7 ie7 end7 d7 ts6 ie6 end6 d6 ts5 ie5 end5 d5 ts4 ie4 end4 d4 ts3 ie3 end3 d3 ts2 ie2 end2 d2 ts1 ie1 end1 d1 ts0 ie0 end0 d0
lm3s817 data sheet may 4, 2007 227 preliminary 24 d6 r/w 0 same definition as d7 but used during the seventh sample. 23 ts5 r/w 0 same definition as ts7 but used during the sixth sample. 22 ie5 r/w 0 same definition as ie7 but used during the sixth sample. 21 end5 r/w 0 same definition as end7 but used during the sixth sample. 20 d5 r/w 0 same definition as d7 but used during the sixth sample. 19 ts4 r/w 0 same definition as ts7 but used during the fifth sample. 18 ie4 r/w 0 same definition as ie7 but used during the fifth sample. 17 end4 r/w 0 same definition as end7 but used during the fifth sample. 16 d4 r/w 0 same definition as d7 but used during the fifth sample. 15 ts3 r/w 0 same definition as ts7 but used during the fourth sample. 14 ie3 r/w 0 same definition as ie7 but used during the fourth sample. 13 end3 r/w 0 same definition as end7 but used during the fourth sample. 12 d3 r/w 0 same definition as d7 but used during the fourth sample. 11 ts2 r/w 0 same definition as ts7 but used during the third sample. 10 ie2 r/w 0 same definition as ie7 but used during the third sample. 9 end2 r/w 0 same definition as end7 but used during the third sample. 8 d2 r/w 0 same definition as d7 but used during the third sample. 7 ts1 r/w 0 same definition as ts7 but used during the second sample. 6 ie1 r/w 0 same definition as ie7 but used during the second sample. 5 end1 r/w 0 same definition as end7 but used during the second sample. 4 d1 r/w 0 same definition as d7 but used during the second sample. 3 ts0 r/w 0 same definition as ts7 but used during the first sample. 2 ie0 r/w 0 same definition as ie7 but used during the first sample. 1 end0 r/w 0 same definition as end7 but used during the first sample. since this sequencer has only one entry, this bit must be set. 0 d0 r/w 0 same definition as d7 but used during the first sample. bit/field name type reset description
analog-to-digital converter (adc) 228 may 4, 2007 preliminary register 13: adc sample sequence result fifo 0 (adcssfifo0), offset 0x048 this register contains the conversion result s for samples collected with sample sequencer 0. reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the fifo is empty. if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcostat and adcustat registers. bit/field name type reset description 31:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9:0 data ro 0 conversion result data. reserved ro 0 adc sample sequence result fifo 0 (adcssfifo0) offset 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved data
lm3s817 data sheet may 4, 2007 229 preliminary register 14: adc sample sequence fifo 0 status (adcssfstat0), offset 0x04c this register provides a window into the sample sequencer fifo 0, providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo. bit/field name type reset description 31:13 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 12 full ro 0 when set, indicates that the fifo is currently full. 11:9 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 8 empty ro 1 when set, indicates that the fifo is currently empty. 7:4 hptr ro 0 this field contains the current "head" pointer index for the fifo, that is, the next entry to be written. 3:0 tptr ro 0 this field contains the current "tail" pointer index for the fifo, that is, the next entry to be read. reserved reserved full empty hptr tptr ro 0 adc sample sequence fifo 0 status (adcssfstat0) offset 0x04c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000100000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved
analog-to-digital converter (adc) 230 may 4, 2007 preliminary register 15: adc sample sequence input mu ltiplexer select 1 (adcssmux1), offset 0x060 this register defines the analog input configurat ion for each sample in a sequence executed with sample sequencer 1. this register is 16-bits wide and contains informat ion for four possible samples. this register?s bit fields are as shown in the diagram below. bit field definitions are the same as those in the adcssmux0 register (see page 224) but are for sample sequencer 1. reserved reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ro 0 reset type 000000000000000 r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w mux3 mux2 mux1 mux0 reserved reserved reserved ro 0 adc sample sequence input multiplexer select 1 (adcssmux1) offset 0x060 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
lm3s817 data sheet may 4, 2007 231 preliminary register 16: adc sample sequence control 1 (adcssctl1), offset 0x064 this register contains the configuration information for each sample for a sequence executed with sample sequencer 1. when configuring a sample sequence, the end bit must be set at some point, whether it be after the first sample , last sample, or any sample in between. this register is 16-bits wide and contains informat ion for four possible samples. this register?s bit fields are as shown in the diagram below. bit field definitions are the same as those in the adcssctl0 register (see page 226) but are for sample sequencer 1. register 17: adc sample sequence result fifo 1 (adcssfifo1), offset 0x068 this register contains the conversion result s for samples collected with sample sequencer 1. reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the fifo is empty. if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcostat and adcustat registers. bit fields and definitions are the same as adcssfifo0 (see page 228) but are for fifo 1. register 18: adc sample sequence fifo 1 status (adcssfstat1), offset 0x06c this register provides a window into the sample sequencer fifo 1, providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo. this register has the same bit fields and definitions as adcssfstat0 (see page 229) but is for fifo 1. ro 0 adc sample sequence control 1 (adcssctl1) offset 0x064 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ts3 ie3 end3 d3 ts2 ie2 end2 d2 ts1 ie1 end1 d1 ts0 ie0 end0 d0 reserved
analog-to-digital converter (adc) 232 may 4, 2007 preliminary register 19: adc sample sequence input mu ltiplexer select 2 (adcssmux2), offset 0x080 this register defines the analog input configurat ion for each sample in a sequence executed with sample sequencer 2. this register is 16-bits wide and contains informat ion for four possible samples. this register?s bit fields are as shown in the diagram below. bit field definitions are the same as those in the adcssmux0 register (see page 224) but are for sample sequencer 2. reserved reserved reserved reserved reserved ro 0 adc sample sequence input multiplexer select 2 (adcssmux2) offset 0x080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 1514131211109876543210 ro 0 reset type 000000000000000 r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w ro r/w r/w r/w mux3 mux2 mux1 mux0
lm3s817 data sheet may 4, 2007 233 preliminary register 20: adc sample sequence control 2 (adcssctl2), offset 0x084 this register contains the configuration information for each sample for a sequence executed with sample sequencer 2. when configuring a sample sequence, the end bit must be set at some point, whether it be after the first sample , last sample, or any sample in between. this register is 16-bits wide and contains informat ion for four possible samples. this register?s bit fields are as shown in the diagram below. bit field definitions are the same as those in the adcssctl0 register (see page 226) but are for sample sequencer 2. register 21: adc sample sequence result fifo 2 (adcssfifo2), offset 0x088 this register contains the conversion result s for samples collected with sample sequencer 2. reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the fifo is empty. if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcostat and adcustat registers. bit fields and definitions are the same as adcssfifo0 (see page 228) but are for fifo 2. register 22: adc sample sequence fifo 2 status (adcssfstat2), offset 0x08c this register provides a window into the sample sequencer fifo 2, providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo. this register has the same bit fields and definitions as adcssfstat0 (see page 229) but is for fifo 2. ro 0 adc sample sequence control 2 (adcssctl2) offset 0x084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ts3 ie3 end3 d3 ts2 ie2 end2 d2 ts1 ie1 end1 d1 ts0 ie0 end0 d0 reserved
analog-to-digital converter (adc) 234 may 4, 2007 preliminary register 23: adc sample sequence input multiplexer select 3 (adcssmux3), offset 0x0a0 this register defines the analog input configurat ion for each sample in a sequence executed with sample sequencer 3. this register is 4-bits wide and contains inform ation for one possible sample. this register?s bit fields are as shown in the diagram below. bit field definitions are the same as those in the adcssmux0 register ( see page 224) but are for sample sequencer 3. reserved reserved ro 0 adc sample sequence input multiplexer select 3 (adcssmux3) offset 0x0a0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w mux0
lm3s817 data sheet may 4, 2007 235 preliminary register 24: adc sample sequence control 3 (adcssctl3), offset 0x0a4 this register contains the configuration information for each sample for a sequence executed with sample sequencer 3. the end bit is always set since there is only one sample in this sequencer. this register is 4-bits wide and contains inform ation for one possible sample. this register?s bit fields are as shown in the diagram below. bit field definitions are the same as those in the adcssctl0 register (see page 226) but are for sample sequencer 3. register 25: adc sample se quence result fifo 3 (adcssfifo3), offset 0x0a8 this register contains the conversion result s for samples collected with sample sequencer 3. reads of this register return the conversion result data. if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcostat and adcustat registers. bit fields and definitions are the same as adcssfifo0 (see page 228) but are for fifo 3. register 26: adc sample sequence fifo 3 status (adcssfstat3), offset 0x0ac this register provides a window into the sample sequencer fifo 3, providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo. this register has the same bit fields and definitions as adcssfstat0 (see page 229) but is for fifo 3. reserved ro 0 adc sample sequence control 3 (adcssctl3) offset 0x0a4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000010 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w ts0 ie0 end0 d0 reserved
analog-to-digital converter (adc) 236 may 4, 2007 preliminary register 27: adc test mode loopback (adctmlb), offset 0x100 this register provides loopback operation within the digital logic of the adc, which can be useful in debugging software without having to provide actual analog stimulus. this test mode is entered by writing a value of 0x00000001 to this register. when data is read from the fifo in loopback mode, the read-only portion of this register is returned. bit/field name type reset description read-only register 31:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9:6 cnt ro 0 continuous sample counter that is initialized to 0 and counts each sample as it processed. this helps provide a unique value for the data received. 5 cont ro 0 when set, indicates that this is a continuation sample. for example if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 4 diff ro 0 when set, indicates that this was to be a differential sample. 3 ts ro 0 when set, indicates that this was to be a temperature sensor sample. 2:0 mux ro 0 indicate which analog input was to be sampled. ro 0 adc test mode loopback (adctmlb): read offset 0x100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved reserved 15 14 13 12 11 10 9876543210 ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro cont cnt diff ts mux ro 0 adc test mode loopback (adctmlb):write offset 0x100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved reserved 15 14 13 12 11 10 9876543210 ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro wo lb
lm3s817 data sheet may 4, 2007 237 preliminary write-only register 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 lb wo 0 when set, forces a loopback within the digital block to provide information on input and unique numbering. the 10-bit loopback data is defined as shown in the read for bits 9:0 below. bit/field name type reset description
universal asynchronous receivers/transmitters (uarts) 238 may 4, 2007 preliminary 12 universal asynchronous receivers/transmitters (uarts) the universal asynchronous receivers/transm itters (uarts) provide fully programmable, 16c550-type serial interface char acteristics. the lm3s817 controller is equipped with two uart modules. each uart has the following features: ? separate transmit and receive fifos ? programmable fifo length, including 1-byte deep operation providing conventional double-buffered interface ? fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ? programmable baud-rate generator allowing rates up to 460.8 kbps ? standard asynchronous communication bits for start, stop and parity ? false start bit detection ? line-break generation and detection ? fully programmable serial interface characteristics: ? 5, 6, 7, or 8 data bits ? even, odd, stick, or no-par ity bit generation/detection ? 1 or 2 stop bit generation
lm3s817 data sheet may 4, 2007 239 preliminary 12.1 block diagram figure 12-1. uart module block diagram 12.2 functional description the stellaris uart performs the functions of para llel-to-serial and serial-t o-parallel conversions. it is similar in functionality to a 16c550 uart, but is not register compatible. the uart is configured for transmit and/or receive via the txe and rxe bits of the uart control (uartctl) register (see page 255). transmit and receive are both enabled out of reset. before any control registers are programmed, the uart must be disabled by clearing the uarten bit in uartctl . if the uart is disabled during a tx or rx operation, the current transaction is completed prior to the uart stopping. 12.2.1 transmit/receive logic the transmit logic performs paralle l-to-serial conversion on the data read from the transmit fifo. the control logic outputs the serial bit stream beginning with a start bit, and followed by the data receiver transmitter system clock control / status uartrsr/ecr uartfr uartlcrh uartctl interrupt control uartifls uartim uartmis uartris uarticr baud rate generator uartibrd uartfbrd identification registers uartpcellid0 uartpcellid1 uartpcellid2 uartpcellid3 uartperiphid0 uartperiphid1 uartperiphid2 uartperiphid3 uart periphid4 uartperiphid5 uartperiphid6 uartperiphid7 uartdr txfifo 16x8 . . . rxfifo 16x8 . . . interrupt untx unrx
universal asynchronous receivers/transmitters (uarts) 240 may 4, 2007 preliminary bits (lsb first), parity bit, and the stop bits according to the programmed configuration in the control registers. see figure 12-2 for details. the receive logic performs serial -to-parallel conversion on the received bit stream after a valid start pulse has been detected. overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive fifo. figure 12-2. uart character frame 12.2.2 baud-rate generation the baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. the number formed by these two values is used by the baud-rate generator to determine the bit period. having a fractional baud-rate divider allows the uart to generate all the standard baud rates. the 16-bit integer is loaded through the uart integer baud-rate divisor (uartibrd) register (see page 251) and the 6-bit fractional part is loaded with the uart fractional baud-rate divisor (uartfbrd) register (see page 252). the baud-rate divisor (brd) has the following relationship to the system clock (where brdi is the integer part of the brd and brdf is the fractional part, separated by a decimal place.): brd = brdi + brdf = sysclk / (16 * baud rate) the 6-bit fractional number (that is to be loaded into the divfrac bit field in the uartfbrd register) can be calculated by taking the fractional part of the baud-ra te divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: uartfbrd[divfrac] = integer(brdf * 64 + 0.5) the uart generates an internal baud-rate refere nce clock at 16x the baud-rate (referred to as baud16 ). this reference clock is divi ded by 16 to generate the transmit clock, and is used for error detection during receive operations. along with the uart line control, high byte (uartlcrh) register (see page 253), the uartibrd and uartfbrd registers form an internal 30-bit regi ster. this internal register is only updated when a write operation to uartlcrh is performed, so any changes to the baud-rate divisor must be followed by a write to the uartlcrh register for the changes to take effect. to update the baud-rate registers, there are four possible sequences: ? uartibrd write, uartfbrd write, and uartlcrh write ? uartfbrd write, uartibrd write, and uartlcrh write ? uartibrd write and uartlcrh write ? uartfbrd write and uartlcrh write 1 0 5-8 data bits lsb msb parity bit if enabled 1-2 stop bits untx n start
lm3s817 data sheet may 4, 2007 241 preliminary 12.2.3 data transmission data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the uart is enabled, it causes a data frame to start transmitting with the parameters indicated in the uartlcrh register. data continues to be transmitted until there is no data left in the transmit fifo. the busy bit in the uart flag (uartfr) register (see page 249) is asserted as soon as data is written to the transmit fifo (that is, if the fifo is non-empty) and remains asserted while data is being transmitted. the busy bit is negated only when the transmit fifo is empty, and the last character has been transmitted from the shift register, including the stop bits. the uart can indicate that it is busy even though the uart may no longer be enabled. when the receiver is idle (u0rx or u1rx is continuously 1) and the data input goes low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of baud16 (described in ?transmit/receive logic? on page 239). the start bit is valid if u0rx or u1rx is still low on the eighth cycle of baud16 , otherwise a false start bit is detected and it is ignored. start bit errors can be viewed in the uart receive status (uartrsr) register (see page 247). if the start bit was valid, successive data bits are sampled on every 16th cycle of baud16 (that is, one bit period later) according to the programmed length of the data characters. the parity bit is then checked if parity mode was enabled. data length and parity are defined in the uartlcrh register. lastly, a valid stop bit is conf irmed if u0rx or u1rx is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that word. 12.2.4 fifo operation the uart has two 16-entry fifos; one for transmit and one for receive. both fifos are accessed via the uart data (uartdr) register (see page 245). read operations of the uartdr register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the tr ansmit fifo. out of reset, both fifos are disabled and act as 1-byte-deep holding registers. the fifos are enabled by setting the fen bit in uartlcrh (page 253). fifo status can be monitored via the uart flag (uartfr) register (see page 249) and the uart receive status (uartrsr) register. hardware monitors empty, full and overrun conditions. the uartfr register contains empty and full flags ( txfe , txff , rxfe and rxff bits) and the uartrsr register shows overrun status via the oe bit. the trigger points at which the fifos generate interrupts is controlled via the uart interrupt fifo level select (uartifls) register (see page 256). both fifos can be individually configured to trigger interrupts at different levels. available configurations in clude 1/8, 1/4, 1/2, 3/4 and 7/8. for example, if the 1/ 4 option is selected for the receive fifo, the uart generates a receive interrupt after 4 data bytes are received. out of reset, both fifos are configured to trigger an interrupt at the 1/2 mark. 12.2.5 interrupts the uart can generate interrupts when the following conditions are observed: ? overrun error ? break error ? parity error ? framing error
universal asynchronous receivers/transmitters (uarts) 242 may 4, 2007 preliminary ? receive timeout ? transmit (when condition defined in the txiflsel bit in the uartifls register is met) ? receive (when condition defined in the rxiflsel bit in the uartifls register is met) all of the interrupt events are ored together befor e being sent to the interrupt controller, so the uart can only generate a single interrupt request to the controller at any given time. software can service multiple interrupt events in a sing le interrupt service routine by reading the uart masked interrupt status (uartmis) register (see page 260). the interrupt events that can trigger a controller-level interrupt are defined in the uart interrupt mask (uartim ) register (see page 257) by setting the corresponding im bit to 1. if interrupts are not used, the raw interrupt status is always visible via the uart raw interrupt status (uartris) register (see page 259). interrupts are always cleared (for both the uartmis and uartris registers) by setting the corresponding bit in the uart interrupt clear (uarticr) register (see page 261). 12.2.6 loopback operation the uart can be placed into an internal loopback mode for diagnostic or debug work. this is accomplished by setting the lbe bit in the uartctl register (see page 255). in loopback mode, data transmitted on the u0tx output is received on the u0rx input, and data transmitted on u1tx is received on u1rx. 12.3 initialization and configuration to use the uarts, the peripheral cl ock must be enabled by setting the uart0 or uart1 bits in the rcgc1 register. this section discusses the steps that are required for using a uart module. for this example, the system clock is assumed to be 20 mhz and the desired uart configuration is: ? 115200 baud rate ? data length of 8 bits ? one stop bit ? no parity ? fifos disabled ? no interrupts the first thing to consider when programming th e uart is the baud-rate divisor (brd), since the uartibrd and uartfbrd registers must be written before the uartlcrh register. using the equation described in ?baud-rate generation? on page 240, the brd can be calculated: brd = 20,000,000 / (16 * 115,200) = 10.8507 which means that the divint field of the uartibrd register (see page 251) should be set to 10. the value to be loaded into the uartfbrd register (see page 252) is calculated by the equation: uartfbrd[divfrac] = integer(0.8507 * 64 + 0.5) = 54 with the brd values in hand, the uart configur ation is written to the module in the following order: 1. disable the uart by clearing the uarten bit in the uartctl register. 2. write the integer portion of the brd to the uartibrd register.
lm3s817 data sheet may 4, 2007 243 preliminary 3. write the fractional portion of the brd to the uartfbrd register. 4. write the desired serial parameters to the uartlcrh register (in this case, a value of 0x00000060). 5. enable the uart by setting the uarten bit in the uartctl register. 12.4 register map table 12-1 lists the uart registers. the offset lis ted is a hexadecimal increment to the register?s address, relative to that uart?s base address: ? uart0: 0x4000c000 ? uart1: 0x4000d000 note: the uart must be disabled (see the uarten bit in the uartctl register on page 255) before any of the control registers are reprogrammed. when the uart is disabled during a tx or rx operation, the current transacti on is completed prior to the uart stopping. table 12-1. uart register map offset name reset type description see page 0x000 uartdr 0x00000000 r/w data 245 0x004 uartrsr uartecr 0x00000000 r/w receive status (read) error clear (write) 247 0x018 uartfr 0x00000090 ro flag register (read only) 249 0x024 uartibrd 0x00000000 r/w int eger baud-rate divisor 251 0x028 uartfbrd 0x00000000 r/w fractional baud-rate divisor 252 0x02c uartlcrh 0x00000000 r/w line control register, high byte 253 0x030 uartctl 0x00000300 r/w control register 255 0x034 uartifls 0x00000012 r/w inte rrupt fifo level select 256 0x038 uartim 0x00000000 r/w interrupt mask 257 0x03c uartris 0x0000000f ro raw interrupt status 259 0x040 uartmis 0x00000000 ro masked interrupt status 260 0x044 uarticr 0x00000000 w1c interrupt clear 261 0xfd0 uartperiphid4 0x00000000 ro pe ripheral identification 4 262 0xfd4 uartperiphid5 0x00000000 ro pe ripheral identification 5 263 0xfd8 uartperiphid6 0x00000000 ro pe ripheral identification 6 264 0xfdc uartperiphid7 0x00000000 ro pe ripheral identification 7 265 0xfe0 uartperiphid0 0x00000011 ro p eripheral identification 0 266 0xfe4 uartperiphid1 0x00000000 ro pe ripheral identification 1 267 0xfe8 uartperiphid2 0x00000018 ro pe ripheral identification 2 268
universal asynchronous receivers/transmitters (uarts) 244 may 4, 2007 preliminary 12.5 register descriptions the remainder of this section lists and describes the uart registers, in numerical order by address offset. 0xfec uartperiphid3 0x00000001 ro pe ripheral identification 3 269 0xff0 uartpcellid0 0x0000000d ro primecell identification 0 270 0xff4 uartpcellid1 0x000000f0 ro primecell identification 1 271 0xff8 uartpcellid2 0x00000005 ro primecell identification 2 272 0xffc uartpcellid3 0x000000b1 ro primecell identification 3 273 table 12-1. uart register map (continued) offset name reset type description see page
lm3s817 data sheet may 4, 2007 245 preliminary register 1: uart data (uartdr), offset 0x000 this register is the data register (the interface to the fifos). when fifos are enabled, data writte n to this location is pushed on to the transmit fifo. if fifos are disabled, data is stored in the transmitter ho lding register (the bottom word of the transmit fifo). a write to this register init iates a transmission from the uart. for received data, if the fifo is enabled, the data byte and the 4-bit status (break, frame, parity and overrun) is pushed onto the 12-bit wide receiv e fifo. if fifos are disabled, the data byte and status are stored in the receiving holding regist er (the bottom word of the receive fifo). the received data can be retrieved by reading this register. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11 oe ro 0 uart overrun error 1=new data was received when the fifo was full, resulting in data loss. 0=there has been no data loss due to a fifo overrun. 10 be ro 0 uart break error this bit is set to 1 when a break condition is detected, indicating that the receive data input was held low for longer than a full- word transmission time (defined as start, data, parity, and stop bits). in fifo mode, this error is a ssociated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 9 pe ro 0 uart parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. in fifo mode, this error is a ssociated with the character at the top of the fifo. reserved ro 0 uart data (uartdr) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w fe reserved data pe be oe
universal asynchronous receivers/transmitters (uarts) 246 may 4, 2007 preliminary 8 fe ro 0 uart framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 7:0 data r/w 0 when written, the data that is to be transmitted via the uart. when read, the data that was received by the uart. bit/field name type reset description
lm3s817 data sheet may 4, 2007 247 preliminary register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 the uartrsr/uartecr register is the receive status register/error clear register. in addition to the uartdr register, receive status can also be read from the uartrsr register. if the status is read from this regi ster, then the status information corresponds to the entry read from uartdr prior to reading uartrsr . the status information for overrun is set immediately when an overrun condition occurs. a write of any value to the uartecr register clears the framing, parity, break, and overrun errors. all the bits are cleared to 0 on reset. bit/field name type reset description read-only receive status (uartrsr) register 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. the uartrsr register cannot be written. 3 oe ro 0 uart overrun error when this bit is set to 1, data is received and the fifo is already full. this bit is cleared to 0 by a write to uartecr . the fifo contents remain valid since no further data is written when the fifo is full, only the c ontents of the shift register are overwritten. the cpu must now read the data in order to empty the fifo. reserved wo 0 uart error clear (uartecr): write offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo 0 reset type 000000000000000 wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo reserved data reserved ro 0 uart receive status (uartrsr): read offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved oe be pe fe
universal asynchronous receivers/transmitters (uarts) 248 may 4, 2007 preliminary 2 be ro 0 uart break error this bit is set to 1 when a break condition is detected, indicating that the received data input was held low for longer than a full- word transmission time (defined as start, data, parity, and stop bits). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is a ssociated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 1 pe ro 0 uart parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register. this bit is cleared to 0 by a write to uartecr . 0 fe ro 0 uart framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is a ssociated with the character at the top of the fifo. write-only error clear (uartecr) register 31:8 reserved wo 0 reserved bits return an indeterminate value, and should never be changed. 7:0 data wo 0 a write to this register of any data clears the framing, parity, break and overrun flags. bit/field name type reset description
lm3s817 data sheet may 4, 2007 249 preliminary register 3: uart flag (uartfr), offset 0x018 the uartfr register is the flag register. after reset, the txff , rxff , and busy bits are 0, and txfe and rxfe bits are 1. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7 txfe ro 1 uart transmit fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled ( fen is 0), this bit is set when the transmit holding register is empty. if the fifo is enabled ( fen is 1), this bit is set when the transmit fifo is empty. 6 rxff ro 0 uart receive fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the receive holding register is full. if the fifo is enabled, this bit is set when the receive fifo is full. 5 txff ro 0 uart transmit fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the transmit holding register is full. if the fifo is enabled, this bit is set when the transmit fifo is full. reserved ro 0 uart flag (uartfr) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000 10010000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved txfe rxff txff rxfe busy reserved
universal asynchronous receivers/transmitters (uarts) 250 may 4, 2007 preliminary 4 rxfe ro 1 uart receive fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register. if the fifo is disabled, this bit is set when the receive holding register is empty. if the fifo is enabled, this bit is set when the receive fifo is empty. 3 busy ro 0 uart busy when this bit is 1, the uart is busy transmitting data. this bit remains set until the complete byte, including all stop bits, has been sent from the shift register. this bit is set as soon as the transmit fifo becomes non-empty (regardless of whether uart is enabled). 2:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. bit/field name type reset description
lm3s817 data sheet may 4, 2007 251 preliminary register 4: uart integer baud-r ate divisor (uarti brd), offset 0x024 the uartibrd register is the integer part of the baud-r ate divisor value. all the bits are cleared on reset. the minimum possible divide ratio is 1 (when uartibrd =0), in which case the uartfbrd register is ignored. when changing the uartibrd register, the new value does not take effect until transmission/reception of the cu rrent character is comple te. any chan ges to the baud-rate divisor must be followed by a write to the uartlcrh register. see ?baud-rate generation? on page 240 for configuration details. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 divint r/w 0x0000 integer baud-rate divisor ro 0 uart integer baud-rate divisor offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved divint
universal asynchronous receivers/transmitters (uarts) 252 may 4, 2007 preliminary register 5: uart fractional baud-r ate divisor (uartfbrd), offset 0x028 the uartfbrd register is the fractional part of the baud-rate divisor value. all the bits are cleared on reset. when changing the uartfbrd register, the new value does not take effect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register. see ?baud-rate generation? on page 240 for configuration details. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:0 divfrac r/w 0x00 fractional baud-rate divisor reserved ro 0 uart fractional baud-rate divisor (uartfbrd) offset 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved divfrac
lm3s817 data sheet may 4, 2007 253 preliminary register 6: uart line control (uartlcrh), offset 0x02c the uartlcrh register is the line control register. serial parameters such as data length, parity and stop bit selection are implemented in this register. when updating the baud-rate divisor ( uartibrd and/or uartifrd ), the uartlcrh register must also be written. the write strobe for th e baud-rate divisor registers is tied to the uartlcrh register. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7 sps r/w 0 uart stick parity select when bits 1, 2 and 7 of uartlcrh are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 6:5 wlen r/w 0 uart word length the bits indicate the number of data bits transmitted or received in a frame as follows: 0x3: 8 bits 0x2: 7 bits 0x1: 6 bits 0x0: 5 bits (default) 4 fen r/w 0 uart enable fifos if this bit is set to 1, transmit and receive fifo buffers are enabled (fifo mode). when cleared to 0, fifos are disabled (character mode). the fifos become 1-byte-deep holding registers. 3 stp2 r/w 0 uart two stop bits select if this bit is set to 1, two stop bi ts are transmitted at the end of a frame. the receive logic does not check for two stop bits being received. reserved ro 0 uart line control (uartlcrh) offset 0x02c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w sps reserved wlen fen stp2 eps pen brk
universal asynchronous receivers/transmitters (uarts) 254 may 4, 2007 preliminary 2 eps r/w 0 uart even parity select if this bit is set to 1, even parity generation and checking is performed during transmission an d reception, which checks for an even number of 1s in data and parity bits. when cleared to 0, then odd parity is performed, which checks for an odd number of 1s. this bit has no effect when parity is disabled by the pen bit. 1 pen r/w 0 uart parity enable if this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 brk r/w 0 uart send break if this bit is set to 1, a low le vel is continually output on the untx output, after completing transmission of the current character. for the proper execution of th e break command, the software must set this bit for at least two frames (character periods). for normal use, this bit must be cleared to 0. bit/field name type reset description
lm3s817 data sheet may 4, 2007 255 preliminary register 7: uart contro l (uartctl), offset 0x030 the uartctl register is the control register. all the bits are cleared on reset except for the transmit enable (txe) and receive enable (rxe) bits, which are set to 1. to enable the uart module, the uarten bit must be set to 1. if so ftware requires a configuration change in the module, the uarten bit must be cleared before the configuration changes are written. if the uart is disabled during a transmit or receive operation, the current transaction is completed prior to the uart stopping. bit/field name type reset description 31:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9 rxe r/w 1 uart receive enable if this bit is set to 1, the rece ive section of the uart is enabled. when the uart is disabled in the middle of a receive, it completes the current character before stopping. 8 txe r/w 1 uart transmit enable if this bit is set to 1, the transmit section of the uart is enabled. when the uart is disabled in the middle of a transmission, it completes the current character before stopping. 7 lbe r/w 0 uart loop back enable if this bit is set to 1, the untx path is fed through the unrx path. 6:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 uarten r/w 0 uart enable if this bit is set to 1, the uart is enabled. when the uart is disabled in the middle of transmission or reception, it completes the current character before stopping. ro 0 uart control (uartcr) offset 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000001100000000 ro ro ro ro ro r/w r/w r/w ro ro ro ro ro ro r/w reserved reserved rxe txe lbe uarten reserved
universal asynchronous receivers/transmitters (uarts) 256 may 4, 2007 preliminary register 8: uart interrupt fifo level select (uartifls), offset 0x034 the uartifls register is the interrupt fifo level select register. you can use this register to define the fifo level at which the txris and rxris bits in the uartris register are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the interrupts ar e generated when the fill level progresses th rough the trigger level. for example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receivin g the 9th character. out of reset, the txiflsel and rxiflsel bits are configured so that the fifos trigger an interrupt at the half-way mark. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5:3 rxiflsel r/w 0x2 uart receive interrupt fifo level select the trigger points for the receive interrupt are as follows: 000: rx fifo 1/8 full 001: rx fifo 1/4 full 010: rx fifo 1/2 full (default) 011: rx fifo 3/4 full 100: rx fifo 7/8 full 101-111: reserved 2:0 txiflsel r/w 0x2 uart transmit interrupt fifo level select the trigger points for the transmit interrupt are as follows: 000: tx fifo 1/8 full 001: tx fifo 1/4 full 010: tx fifo 1/2 full (default) 011: tx fifo 3/4 full 100: tx fifo 7/8 full 101-111: reserved reserved ro 0 uart interrupt fifo level select (uartifls) offset 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000010010 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w reserved txiflsel rxiflsel
lm3s817 data sheet may 4, 2007 257 preliminary register 9: uart interrupt mask (uartim), offset 0x038 the uartim register is the interrup t mask set/clear register. on a read, this register gives the current value of the mask on the relevant interrupt. writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oeim r/w 0 uart overrun error interrupt mask on a read, the current mask for the oeim interrupt is returned. setting this bit to 1 promotes the oeim interrupt to the interrupt controller. 9 beim r/w 0 uart break error interrupt mask on a read, the current mask for the beim interrupt is returned. setting this bit to 1 promotes the beim interrupt to the interrupt controller. 8 peim r/w 0 uart parity error interrupt mask on a read, the current mask for the peim interrupt is returned. setting this bit to 1 promotes the peim interrupt to the interrupt controller. 7 feim r/w 0 uart framing error interrupt mask on a read, the current mask for the feim interrupt is returned. setting this bit to 1 promotes the feim interrupt to the interrupt controller. 6 rtim r/w 0 uart receive ti me-out interrupt mask on a read, the current mask for the rtim interrupt is returned. setting this bit to 1 promotes the rtim interrupt to the interrupt controller. reserved ro 0 uart interrupt mask (uartim) offset 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000 0000 ro ro ro ro r/w r/w r/w r/w r/w r/w r/w ro ro ro ro oeim reserved beim peim feim rtim txim rxim reserved
universal asynchronous receivers/transmitters (uarts) 258 may 4, 2007 preliminary 5 txim r/w 0 uart transmit interrupt mask on a read, the current mask for the txim interrupt is returned. setting this bit to 1 promotes the txim interrupt to the interrupt controller. 4 rxim r/w 0 uart receive interrupt mask on a read, the current mask for the rxim interrupt is returned. setting this bit to 1 promotes the rxim interrupt to the interrupt controller. 3:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. bit/field name type reset description
lm3s817 data sheet may 4, 2007 259 preliminary register 10: uart raw interrupt status (uartris), offset 0x03c the uartris register is the raw interrupt status register . on a read, this register gives the current raw status value of the corresponding interrupt. a write has no effect. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oeris ro 0 uart overrun error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 9 beris ro 0 uart break error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 8 peris ro 0 uart parity error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 7 feris ro 0 uart framing error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 6 rtris ro 0 uart receive time-out raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 5 txris ro 0 uart transmit raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 4 rxris ro 0 uart receive raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved ro 0xf this reserved bit is read-only and has a reset value of 0xf. reserved ro 0 uart raw interrupt status (uartris) offset 0x03c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001111 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro oeris reserved beris peris feris rtris txris rxris reserved
universal asynchronous receivers/transmitters (uarts) 260 may 4, 2007 preliminary register 11: uart masked interrupt status (uartmis), offset 0x040 the uartmis register is the masked interrupt status re gister. on a read, this register gives the current masked status value of the corres ponding interrupt. a write has no effect. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oemis ro 0 uart overrun erro r masked interrupt status gives the masked interrupt state of this interrupt. 9 bemis ro 0 uart break error masked interrupt status gives the masked interrupt state of this interrupt. 8 pemis ro 0 uart parity error masked interrupt status gives the masked interrupt state of this interrupt. 7 femis ro 0 uart framing error masked interrupt status gives the masked interrupt state of this interrupt. 6 rtmis ro 0 uart receive time-out masked interrupt status gives the masked interrupt state of this interrupt. 5 txmis ro 0 uart transmit masked interrupt status gives the masked interrupt state of this interrupt. 4 rxmis ro 0 uart receive masked interrupt status gives the masked interrupt state of this interrupt. 3:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved ro 0 uart masked interrupt status (uartmis) offset 0x040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro oemis reserved bemis pemis femis rtmis txmis rxmis reserved
lm3s817 data sheet may 4, 2007 261 preliminary register 12: uart interrupt clear (uarticr), offset 0x044 the uarticr register is the interrupt clear register. on a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enab led) is cleared. a write of 0 has no effect. bit/field name type reset description 31:11 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 10 oeic w1c 0 overrun error interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 9 beic w1c 0 break error interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 8 peic w1c 0 parity error interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 7 feic w1c 0 framing error interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 6 rtic w1c 0 receive time-out interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 5 txic w1c 0 transmit interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 4 rxic w1c 0 receive interrupt clear 0: no effect on the interrupt. 1: clears interrupt. 3:0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved ro 0 uart interrupt clear (uarticr) offset 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro w1c w1c w1c w1c w1c w1c w1c ro ro ro ro oeic reserved beic peic feic rtic txic rxic reserved
universal asynchronous receivers/transmitters (uarts) 262 may 4, 2007 preliminary register 13: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 uart peripheral id register[7:0] reserved ro 0 uart peripheral identification 4 (uartperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
lm3s817 data sheet may 4, 2007 263 preliminary register 14: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 uart peripheral id register[15:8] reserved ro 0 uart peripheral identification 5 (uartperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
universal asynchronous receivers/transmitters (uarts) 264 may 4, 2007 preliminary register 15: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 uart peripheral id register[23:16] reserved ro 0 uart peripheral identification 6 (uartperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
lm3s817 data sheet may 4, 2007 265 preliminary register 16: uart peripheral identification 7 (uartperiphid7), offset 0xfdc the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 uart peripheral id register[31:24] reserved ro 0 uart peripheral identification 7 (uartperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
universal asynchronous receivers/transmitters (uarts) 266 may 4, 2007 preliminary register 17: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x11 uart peripheral id register[7:0] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 0 (uartperiphid0) offset 0xfe0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000010001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
lm3s817 data sheet may 4, 2007 267 preliminary register 18: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x00 uart peripheral id register[15:8] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 1 (uartperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
universal asynchronous receivers/transmitters (uarts) 268 may 4, 2007 preliminary register 19: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 uart peripheral id register[23:16] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 2 (uartperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
lm3s817 data sheet may 4, 2007 269 preliminary register 20: uart peripheral identification 3 (uartperiphid3), offset 0xfec the uartperiphidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x01 uart peripheral id register[31:24] can be used by software to identify the presence of this peripheral. reserved ro 0 uart peripheral identification 3 (uartperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
universal asynchronous receivers/transmitters (uarts) 270 may 4, 2007 preliminary register 21: uart primec ell identification 0 (uar tpcellid0), offset 0xff0 the uartpcellidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d uart primecell id register[7:0] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 0 (uartpcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
lm3s817 data sheet may 4, 2007 271 preliminary register 22: uart primec ell identification 1 (uar tpcellid1), offset 0xff4 the uartpcellidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 uart primecell id register[15:8] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 1 (uartpcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
universal asynchronous receivers/transmitters (uarts) 272 may 4, 2007 preliminary register 23: uart primec ell identification 2 (uar tpcellid2), offset 0xff8 the uartpcellidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 uart primecell id register[23:16] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 2 (uartpcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
lm3s817 data sheet may 4, 2007 273 preliminary register 24: uart primec ell identification 3 (uar tpcellid3), offset 0xffc the uartpcellidn registers are hard-coded and the fiel ds within the registers determine the reset values. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 uart primecell id register[31:24] provides software a standard cross-peripheral identification system. reserved ro 0 uart primecell identification 3 (uartpcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
synchronous serial interface (ssi) 274 may 4, 2007 preliminary 13 synchronous serial interface (ssi) the stellaris synchronous serial interface (ssi) is a master or slave interface for synchronous serial communication with peripheral devices t hat have either freescale spi, microwire, or texas instruments synchronous serial interfaces. the stellaris ssi has the following features: ? master or slave operation ? programmable clock bit rate and prescale ? separate transmit and receive fifos, 16 bits wide, 8 locations deep ? programmable interface operation for freescale spi, microwire, or texas instruments synchronous serial interfaces ? programmable data frame size from 4 to 16 bits ? internal loopback test mode for diagnostic/debug testing 13.1 block diagram figure 13-1. ssi module block diagram transmit / receive logic clock prescaler ssicpsr control / status ssicr0 ssicr1 ssisr interrupt control ssiim ssimis ssiris ssiicr ssidr txfifo 8 x 16 . . . rxfifo 8 x 16 . . . system clock ssitx ssirx ssiclk ssifss interrupt identification registers ssipcellid0 ssiperiphid 0 ssiperiphid 4 ssipcellid1 ssiperiphid 1 ssiperiphid 5 ssipcellid2 ssiperiphid 2 ssiperiphid 6 ssipcellid3 ssiperiphid 3 ssiperiphid 7
lm3s817 data sheet may 4, 2007 275 preliminary 13.2 functional description the ssi performs serial-to-para llel conversion on data received from a peripheral device. the cpu accesses data, control, and status information. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 13.2.1 bit rate generation the ssi includes a programmable bit rate clock di vider and prescaler to generate the serial output clock. bit rates are supported to 2 mhz and high er, although maximum bit rate is determined by peripheral devices. the serial bit rate is derived by dividing down the 50-mhz input clock. the clock is first divided by an even prescale value cpsdvsr from 2 to 254, which is programmed in the ssi clock prescale (ssicpsr) register (see page 292). the clock is further divided by a value from 1 to 256, which is 1 + scr , where scr is the value programmed in the ssi control0 (ssicr0) register (see page 286). the frequency of the output clock ssiclk is defined by: fssiclk = fsysclk / (cpsdvsr * (1 + scr)) note that although the ssiclk transmit clock can theoretically be 25 mhz, the module may not be able to operate at that speed. for master mode, t he system clock must be at least two times faster than the ssiclk . for slave mode, the system clock must be at least 12 times faster than the ssiclk . see ?electrical characterist ics? on page 361 to view ssi timing parameters. 13.2.2 fifo operation 13.2.2.1 transmit fifo the common transmit fifo is a 16-bit wide, 8-loca tions deep, first-in, first-out memory buffer. the cpu writes data to the fifo by writing the ssi data (ssidr) register (see page 290), and data is stored in the fifo until it is re ad out by the transmission logic. when configured as a master or a slave, parallel data is written into the transmit fifo prior to serial conversion and transmission to the attach ed slave or master, respectively, through the ssitx pin. 13.2.2.2 receive fifo the common receive fifo is a 16-b it wide, 8-locations deep, first-in, first-out memory buffer. received data from the serial interface is stored in the buffer until read out by the cpu, which accesses the read fifo by reading the ssidr register. when configured as a master or slav e, serial data received through the ssirx pin is registered prior to parallel loading into the attached slave or master receive fifo, respectively. 13.2.3 interrupts the ssi can generate interrupts when the following conditions are observed: ? transmit fifo service ? receive fifo service ? receive fifo time-out ? receive fifo overrun
synchronous serial interface (ssi) 276 may 4, 2007 preliminary all of the interrupt events are ored together befor e being sent to the interrupt controller, so the ssi can only generate a single interrupt request to the controller at any given time. you can mask each of the four individual maskable interr upts by setting the appropriate bits in the ssi interrupt mask (ssiim) register (see page 293). setting the approp riate mask bit to 1 enables the interrupt. provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. the transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the fifo trigger levels. the status of the individual interrupt sources can be read from the ssi raw interrupt status (ssiris) and ssi masked interrupt status (ssimis) registers (see page 294 and page 295, respectively). 13.2.4 frame formats each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the msb. there are three basic frame types that can be selected: ? texas instruments synchronous serial ? freescale spi ? microwire for all three formats, the serial clock ( ssiclk ) is held inactive while the ssi is idle, and ssiclk transitions at the programmed frequency only during active transmission or reception of data. the idle state of ssiclk is utilized to provide a receive timeout i ndication that occurs when the receive fifo still contains data after a timeout period. for freescale spi and microwire frame formats, the serial frame ( ssifss ) pin is active low, and is asserted (pulled down) during the entire transmission of the frame. for texas instruments synchron ous serial frame format, the ssifss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. for this frame format, both the ssi and the off- chip slave device drive their out put data on the rising edge of ssiclk , and latch data from the other device on the falling edge. unlike the full-duplex transmission of the other two frame formats, the microwire format uses a special master-slave me ssaging technique, which operates at half-duplex. in this mode, when a frame begins, an 8-bit control message is transmitte d to the off-chip slave. during this transmit, no incoming data is received by the ssi. after the me ssage has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. the returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 13.2.4.1 texas instruments synchronous serial frame format figure 13-2 shows the texas instruments synchronou s serial frame format for a single transmitted frame. figure 13-2. ti synchronous serial frame format (single transfer) ssiclk 4to16bits ssifss ssitx/ssirx msb lsb
lm3s817 data sheet may 4, 2007 277 preliminary in this mode, ssiclk and ssifss are forced low, and the transmit data line ssitx is tristated whenever the ssi is idle. once the bottom entry of the transmit fifo contains data, ssifss is pulsed high for one ssiclk period. the value to be transmitt ed is also transferred from the transmit fifo to the serial shift register of t he transmit logic. on the next rising edge of ssiclk , the msb of the 4 to 16-bit data frame is shifted out on the ssitx pin. likewise, the msb of the received data is shifted onto the ssirx pin by the off-chip serial slave device. both the ssi and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each ssiclk . the received data is transferre d from the serial shifter to the receive fifo on the first rising edge of ssiclk after the lsb has been latched. figure 13-3 shows the texas inst ruments synchronous serial frame format when back-to-back frames are transmitted. figure 13-3. ti synchronous serial frame format (continuous transfer) 13.2.4.2 freescale spi frame format the freescale spi interface is a four-wire interface where the ssifss signal behaves as a slave select. the main feature of the freescale spi form at is that the inactive state and phase of the ssiclk signal are programmable through the spo and sph bits within the ssiscr0 control register. spo clock polarity bit when the spo clock polarity control bit is low, it pr oduces a steady state low value on the ssiclk pin. if the spo bit is high, a steady state high value is placed on the ssiclk pin when data is not being transferred. sph phase control bit the sph phase control bit selects the clock edge that ca ptures data and allows it to change state. it has the most impact on the first bit transmitt ed by either allowing or not allowing a clock transition before the first data capture edge. when the sph phase control bit is low, data is captured on the first clock edge transition. if the sph bit is high, data is captured on the second clock edge transition. 13.2.4.3 freescale spi frame format with spo=0 and sph=0 single and continuous transmission signal se quences for freescale spi format with spo=0 and sph=0 are shown in figure 13-4 and figure 13-5. msb lsb 4to16bits ssiclk ssifss ssitx/ssirx
synchronous serial interface (ssi) 278 may 4, 2007 preliminary figure 13-4. freescale spi format (single transfer) with spo=0 and sph=0 figure 13-5. freescale spi format (continuous transfer) with spo=0 and sph=0 in this configuration, during idle periods: ? ssiclk is forced low ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data withi n the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. this causes slave data to be enabled onto the ssirx input line of the master. the master ssitx output pad is enabled. one half ssiclk period later, valid master data is transferred to the ssitx pin. now that both the master and slave data have been set, the ssiclk master clock pin goes high after one further half ssiclk period. the data is now captured on the rising a nd propagated on the falling edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer. this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 13.2.4.4 freescale spi frame format with spo=0 and sph=1 the transfer signal sequence for freescale spi format with spo=0 and sph=1 is shown in figure 13-6, which covers both single and continuous transfers. 4to16bits ssiclk ssifss ssirx q ssitx msb msb lsb lsb ssiclk ssifss ssirx lsb ssitx msb lsb 4to16bits lsb msb msb msb lsb
lm3s817 data sheet may 4, 2007 279 preliminary figure 13-6. freescale spi frame format with spo=0 and sph=1 in this configuration, during idle periods: ? ssiclk is forced low ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data withi n the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output is enabled. after a further one half ssiclk period, both master and slave valid data is enabled onto their respective transmission lines. at the same time, the ssiclk is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transfer, after all bits have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer. 13.2.4.5 freescale spi frame format with spo=1 and sph=0 single and continuous transmission signal se quences for freescale spi format with spo=1 and sph=0 are shown in figure 13-7 and figure 13-8. figure 13-7. freescale spi frame format (single transfer) with spo=1 and sph=0 4to16bits ssiclk ssifss ssirx ssitx q msb q msb lsb lsb 4to16bits ssiclk ssifss ssirx ssitx q msb msb lsb lsb
synchronous serial interface (ssi) 280 may 4, 2007 preliminary figure 13-8. freescale spi frame format (continuous transfer) with spo=1 and sph=0 in this configuration, during idle periods: ? ssiclk is forced high ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data withi n the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low, which causes slave data to be immediately transferred onto the ssirx line of the master. the master ssitx output pad is enabled. one half period later, valid master data is transferred to the ssitx line. now that both the master and slave data have been set, the ssiclk master clock pin becomes low after one further half ssiclk period. this means that data is captured on the falling e dges and propagat ed on the rising edges of the ssiclk signal. in the case of a single word tran smission, after all bits of the data word are transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however, in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer. this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. 13.2.4.6 freescale spi frame format with spo=1 and sph=1 the transfer signal sequence for freescale spi format with spo=1 and sph=1 is shown in figure 13-9, which covers both single and continuous transfers. figure 13-9. freescale spi frame format with spo=1 and sph=1 note: q is undefined in figure 13-9. ssiclk ssifss ssitx/ssirx msb lsb 4to16bits lsb msb 4to16bits ssiclk ssifss ssirx ssitx q q msb msb lsb lsb
lm3s817 data sheet may 4, 2007 281 preliminary in this configuration, during idle periods: ? ssiclk is forced high ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ? when the ssi is configured as a master, it enables the ssiclk pad ? when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data withi n the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low. the master ssitx output pad is enabled. after a further one-half ssiclk period, both master and slave data are enabled onto their respective transmission lines. at the same time, ssiclk is enabled with a falling edge transition. data is then captured on the rising edge s and propagated on th e falling edges of the ssiclk signal. after all bits have been transferred, in the case of a single word transmission, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transmissions, the ssifss pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer. 13.2.4.7 microwire frame format figure 13-10 shows the microwire frame format, again for a single frame. figure 13-11 shows the same format when back-to-back frames are transmitted. figure 13-10. microwire frame format (single frame) microwire format is very similar to spi forma t, except that transmission is half-duplex instead of full-duplex, using a master-slave message pa ssing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssi to the off-chip slave device. during this transmission, no incoming data is received by the ssi. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ? ssiclk is forced low ? ssifss is forced high ? the transmit data line ssitx is arbitrarily forced low ssiclk ssifss lsb msb ssirx 4to16bits output data 0 ssitx msb lsb 8-bit control
synchronous serial interface (ssi) 282 may 4, 2007 preliminary a transmission is triggered by writing a control byte to the tr ansmit fifo. the falling edge of ssifss causes the value contained in the bottom entr y of the transmit fifo to be transferred to the serial shift register of the transmit logic, and the msb of the 8-bit control frame to be shifted out onto the ssitx pin. ssifss remains low for the duration of the frame transmission. the ssirx pin remains tristated duri ng this transmission. the off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each ssiclk . after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by tr ansmitting data back to the ssi. each bit is driven onto the ssirx line on the falling edge of ssiclk . the ssi in turn latches each bit on the rising edge of ssiclk . at the end of the frame, for single transfers, the ssifss signal is pulled high one clock period after the last bit has been latc hed in the receive serial shifter, which causes the data to be transferr ed to the receive fifo. note: the off-chip slave device can tristate the receive line either on the falling edge of ssiclk after the lsb has been latched by the receive shifter, or when the ssifss pin goes high. for continuous transfers, data transmission begi ns and ends in the same manner as a single transfer. however, the ssifss line is continuously asserted (hel d low) and transmission of data occurs back-to-back. the control byte of the ne xt frame follows directly after the lsb of the received data from the current frame. each of the received values is transferred from the receive shifter on the falling edge of ssiclk , after the lsb of the frame has been latched into the ssi. figure 13-11. microwire frame format (continuous transfer) in the microwire mode, the ssi slave samples the first bit of receive data on the rising edge of ssiclk after ssifss has gone low. masters that drive a free-running ssiclk must ensure that the ssifss signal has sufficient setup and hold margins with respect to the rising edge of ssiclk . figure 13-12 illustrates these se tup and hold time requirem ents. with respect to the ssiclk rising edge on which the first bit of receive dat a is to be sampled by the ssi slave, ssifss must have a setup of at least two times the period of ssiclk on which the ssi operates. with respect to the ssiclk rising edge previous to this edge, ssifss must have a hold of at least one ssiclk period. 8-bit control ssiclk ssifss lsb msb ssirx 4to16bits output data 0 ssitx msb lsb lsb msb
lm3s817 data sheet may 4, 2007 283 preliminary figure 13-12. microwire frame format, ssi fss input setup and hold requirements 13.3 initialization and configuration to use the ssi, its peripheral clock must be enabled by setting the ssi bit in the rcgc1 register. for each of the frame formats, the ssi is configured using the following steps: 1. ensure that the sse bit in the ssicr1 register is disabled before making any configuration changes. 2. select whether the ssi is a master or slave: a. for master operations, set the ssicr1 register to 0x00000000. b. for slave mode (output enabled), set the ssicr1 register to 0x00000004. c. for slave mode (output disabled), set the ssicr1 register to 0x0000000c. 3. configure the clock prescale divisor by writing the ssicpsr register. 4. write the ssicr0 register with the following configuration: ? serial clock rate ( scr ) ? desired clock phase/polarity, if using freescale spi mode ( sph and spo ) ? the protocol mode: freescale spi, ti ssf, microwire ( frf ) ? the data size ( dss ) 5. enable the ssi by setting the sse bit in the ssicr1 register. as an example, assume the ssi must be configured to operate with the following parameters: ? master operation ? freescale spi mode (spo=1, sph=1) ? 1 mbps bit rate ? 8 data bits assuming the system clock is 20 mhz, the bit rate calculation would be: fssiclk = fsysclk / (cpsdvsr * (1 + scr)) ' 1x106 = 20x106 / (cpsdvsr * (1 + scr)) in this case, if cpsdvsr =2, scr must be 9. the configuration sequence would be as follows: 1. ensure that the sse bit in the ssicr1 register is disabled. 2. write the ssicr1 register with a value of 0x00000000. ssiclk ssifss ssirx first rx data to be sam p led b y ssi slave t setup =(2*t ssiclk ) t hold =t ssiclk
synchronous serial interface (ssi) 284 may 4, 2007 preliminary 3. write the ssicpsr register with a value of 0x00000002. 4. write the ssicr0 register with a value of 0x000009c7. 5. the ssi is then enabled by setting the sse bit in the ssicr1 register to 1. 13.4 register map table 13-1 lists the ssi registers. the offset list ed is a hexadecimal increment to the register?s address, relative to the ssi base address of 0x40008000. note: the ssi must be disabled (see the sse bit in the ssicr1 register) before any of the control registers are reprogrammed. table 13-1. ssi register map offset name reset type description see page 0x000 ssicr0 0x00000000 r/w control 0 286 0x004 ssicr1 0x00000000 r/w control 1 288 0x008 ssidr 0x00000000 r/w data 290 0x00c ssisr 0x00000003 ro status 291 0x010 ssicpsr 0x00000000 r/w clock prescale 292 0x014 ssiim 0x00000000 r/w interrupt mask 293 0x018 ssiris 0x00000008 ro raw interrupt status 294 0x01c ssimis 0x00000000 ro masked interrupt status 295 0x020 ssiicr 0x00000000 w1c interrupt clear 296 0xfd0 ssiperiphid4 0x00000000 ro pe ripheral identification 4 297 0xfd4 ssiperiphid5 0x00000000 ro pe ripheral identification 5 298 0xfd8 ssiperiphid6 0x00000000 ro pe ripheral identification 6 299 0xfdc ssiperiphid7 0x00000000 ro pe ripheral identification 7 300 0xfe0 ssiperiphid0 0x00000022 ro pe ripheral identification 0 301 0xfe4 ssiperiphid1 0x00000000 ro pe ripheral identification 1 302 0xfe8 ssiperiphid2 0x00000018 ro pe ripheral identification 2 303 0xfec ssiperiphid3 0x00000001 ro pe ripheral identification 3 304 0xff0 ssipcellid0 0x0000000d ro primecell identification 0 305 0xff4 ssipcellid1 0x000000f0 ro primecell identification 1 306 0xff8 ssipcellid2 0x00000005 ro primecell identification 2 307 0xffc ssipcellid3 0x000000b1 ro primecell identification 3 308
lm3s817 data sheet may 4, 2007 285 preliminary 13.5 register descriptions the remainder of this section lists and describes the ssi registers, in numerical order by address offset.
synchronous serial interface (ssi) 286 may 4, 2007 preliminary register 1: ssi control 0 (ssicr0), offset 0x000 ssicr0 is control register 0 and contains bit fields that control various functions within the ssi module. functionality such as protocol mode, cloc k rate and data size are configured in this register. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:8 scr r/w 0 ssi serial clock rate the value scr is used to generate the transmit and receive bit rate of the ssi. the bit rate is: br= f ssiclk /(cpsdvsr * (1 + scr)) where cpsdvsr is an even value from 2-254 programmed in the ssicpsr register, and scr is a value from 0-255. 7 sph r/w 0 ssi serial clock phase this bit is only applicable to the freescale spi format. the sph control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph bit is 0, data is captured on the first clock edge transition. if sph is 1, data is captured on the second clock edge transition. 6 spo r/w 0 ssi serial clock polarity this bit is only applicable to the freescale spi format. when the spo bit is 0, it produces a steady state low value on the ssiclk pin. if spo is 1, a steady state high value is placed on the ssiclk pin when data is not being transferred. ro 0 ssi control 0 (ssicr0) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved frf dss scr spo sph
lm3s817 data sheet may 4, 2007 287 preliminary 5:4 frf r/w 0 ssi frame format select. the frf values are defined as follows: 3:0 dss r/w 0 ssi data size select the dss values are defined as follows: bit/field name type reset description frf value frame format 00 freescale spi frame format 01 texas instruments synchronous serial frame format 10 microwire frame format 11 reserved dss value data size 0000-0010 reserved 0011 4-bit data 0100 5-bit data 0101 6-bit data 0110 7-bit data 0111 8-bit data 1000 9-bit data 1001 10-bit data 1010 11-bit data 1011 12-bit data 1100 13-bit data 1101 14-bit data 1110 15-bit data 1111 16-bit data
synchronous serial interface (ssi) 288 may 4, 2007 preliminary register 2: ssi control 1 (ssicr1), offset 0x004 ssicr1 is control register 1 and contains bit fields that control various functions within the ssi module. master and slave mode functionality is controlled by this register. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 sod r/w 0 ssi slave mode output disable this bit is relevant only in the slave mode ( ms =1). in multiple-slave systems, it is possible for the ssi master to broadcast a message to all slaves in the system while ensuring that only one slave driv es data onto the serial output line. in such systems, the txd lines from multiple slaves could be tied togethe r. to operate in such a system, the sod bit can be configured so that th e ssi slave does not drive the ssitx pin. 0: ssi can drive ssitx output in slave output mode. 1: ssi must not drive the ssitx output in slave mode. 2 ms r/w 0 ssi master/slave select this bit selects master or slave mode and can be modified only when ssi is disabled ( sse =0). 0: device configured as a master. 1: device configured as a slave. reserved ro 0 ssi control 1 (sscr1) offset 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved lbm sse ms sod
lm3s817 data sheet may 4, 2007 289 preliminary 1 sse r/w 0 ssi synchronous serial port enable setting this bit enables ssi operation. 0: ssi operation disabled. 1: ssi operation enabled. note: this bit must be set to 0 before any control registers are reprogrammed. 0 lbm r/w 0 ssi loopback mode setting this bit enables loopback test mode. 0: normal serial port operation enabled. 1: output of the transmit serial shift register is connected internally to the input of the receive serial shift register. bit/field name type reset description
synchronous serial interface (ssi) 290 may 4, 2007 preliminary register 3: ssi data (ssidr), offset 0x008 ssidr is the data register and is 16-bits wide. when ssidr is read, the entry in the receive fifo (pointed to by the current fifo read pointer) is accessed. as data values are removed by the ssi receive logic from the incoming data frame, they are placed into the entry in the receive fifo (pointed to by the current fifo write pointer). when ssidr is written to, the entry in the transmit fifo (pointed to by the write pointer) is written to. data values are removed from the transmit fifo one value at a time by the transmit logic. it is loaded into the transmit serial shifter, then serially shifted out onto the ssit x pin at the programmed bit rate. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores the unus ed bits. received data less than 16 bits is automatically right-justifie d in the receive buffer. when the ssi is programmed for microwire frame fo rmat, the default size for transmit data is eight bits (the most significant byte is ignored ). the receive data size is controlled by the programmer. the transmit fifo and the rece ive fifo are not cleared even when the sse bit in the ssicr1 register is set to zero. this allows the softwa re to fill the transmit fifo before enabling the ssi. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 data r/w 0 ssi receive/transmit data a read operation reads the rece ive fifo. a write operation writes the transmit fifo. software must right-justify data when the ssi is programmed for a data size that is less than 16 bits. unused bits at the top are ignored by the transmit logic. the receive logic automatically right-justifies the data. data ro 0 ssi data (ssidr) offset 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved
lm3s817 data sheet may 4, 2007 291 preliminary register 4: ssi status (ssisr), offset 0x00c ssisr is a status register that contains bits that indicate the fifo fill status and the ssi busy status. bit/field name type reset description 31:5 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 4 bsy ro 0 ssi busy bit 0: ssi is idle. 1: ssi is currently transmitting a nd/or receiving a frame, or the transmit fifo is not empty. 3 rff ro 0 ssi receive fifo full 0: receive fifo is not full. 1: receive fifo is full. 2 rne ro 0 ssi receive fifo not empty 0: receive fifo is empty. 1: receive fifo is not empty. 1 tnf ro 1 ssi transmit fifo not full 0: transmit fifo is full. 1: transmit fifo is not full. 0 tfe r0 1 ssi transmit fifo empty 0: transmit fifo is not empty. 1: transmit fifo is empty. reserved ro 0 ssi status (ssisr) offset 0x00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000011 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved tfe tnf rne rff bsy
synchronous serial interface (ssi) 292 may 4, 2007 preliminary register 5: ssi clock prescale (ssicpsr), offset 0x010 ssicpsr is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. the value programmed into this register must be an even number between 2 and 254. the least-significant bit of the programmed number is hard-coded to zero. if an odd number is written to this register, data read back from this register has the least-significant bit as zero. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cpsdvsr r/w 0 ssi clock prescale divisor this value must be an even number from 2 to 254, depending on the frequency of ssiclk . the lsb always returns 0 on reads. reserved ro 0 ssi clock prescale (ssicpsr) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w reserved cpsdvsr
lm3s817 data sheet may 4, 2007 293 preliminary register 6: ssi interrupt mask (ssiim), offset 0x014 the ssiim register is the interrupt mask set or clear re gister. it is a read/write register and all bits are cleared to 0 on reset. on a read, this register gives the current value of the mask on the relevant in terrupt. a write of 1 to the particular bit sets the mask, enabling the interrupt to be read. a write of 0 clears the corresponding mask. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 txim r/w 0 ssi transmit fifo interrupt mask 0: tx fifo half-full or less condition interrupt is masked. 1: tx fifo half-full or less co ndition interrupt is not masked. 2 rxim r/w 0 ssi receive fifo interrupt mask 0: rx fifo half-full or more condition interrupt is masked. 1: rx fifo half-full or more condition interrupt is not masked. 1 rtim r/w 0 ssi receive ti me-out interrupt mask 0: rx fifo time-out interrupt is masked. 1: rx fifo time-out interrupt is not masked. 0 rorim r/w 0 ssi receive overrun interrupt mask 0: rx fifo overrun interrupt is masked. 1: rx fifo overrun interrupt is not masked. reserved ro 0 ssi interrupt mask (ssiim) offset 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w reserved rorim rtim rxim txim
synchronous serial interface (ssi) 294 may 4, 2007 preliminary register 7: ssi raw interrupt status (ssiris), offset 0x018 the ssiris register is the raw interrupt status register. on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no effect. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 txris ro 1 ssi transmit fifo raw interrupt status indicates that the transmit fifo is half full or less, when set. 2 rxris ro 0 ssi receive fifo raw interrupt status indicates that the receive fifo is half full or more, when set. 1 rtris ro 0 ssi receive time-out raw interrupt status indicates that the receive time-out has occurred, when set. 0 rorris ro 0 ssi receive overrun raw interrupt status indicates that the receive fifo has overflowed, when set. reserved ro 0 ssi raw interrupt status (ssiris) offset 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved rorris rtris rxris txris
lm3s817 data sheet may 4, 2007 295 preliminary register 8: ssi masked interrupt status (ssimis), offset 0x01c the ssimis register is the masked interrupt status re gister. on a read, this register gives the current masked status value of the corres ponding interrupt. a write has no effect. bit/field name type reset description 31:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3 txmis ro 0 ssi transmit fifo masked interrupt status indicates that the transmit fifo is half full or less, when set. 2 rxmis ro 0 ssi receive fifo masked interrupt status indicates that the receive fifo is half full or more, when set. 1 rtmis ro 0 ssi receive time-out masked interrupt status indicates that the receive time-out has occurred, when set. 0 rormis ro 0 ssi receive ove rrun masked inte rrupt status indicates that the receive fifo has overflowed, when set. reserved ro 0 ssi masked interrupt status (ssimis) offset 0x01c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved rormis rtmis rxmis txmis
synchronous serial interface (ssi) 296 may 4, 2007 preliminary register 9: ssi interrupt cl ear (ssiicr), offset 0x020 the ssiicr register is the interrupt clear register. on a write of 1, the corresponding interrupt is cleared. a write of 0 has no effect. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 rtic w1c 0 ssi receive time-out interrupt clear 0: no effect on interrupt. 1: clears interrupt. 0 roric w1c 0 ssi receive overrun interrupt clear 0: no effect on interrupt. 1: clears interrupt. reserved ro 0 ssi interrupt clear (ssiicr) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 0000000000000 00 ro ro ro ro ro ro ro ro ro ro ro ro ro w1c w1c reserved roric rtic
lm3s817 data sheet may 4, 2007 297 preliminary register 10: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid4 ro 0x00 ssi perip heral id register[7:0] reserved ro 0 ssi peripheral identification 4 (ssiperiphid4) offset 0xfd0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid4
synchronous serial interface (ssi) 298 may 4, 2007 preliminary register 11: ssi peripheral identifica tion 5 (ssiperiphid5), offset 0xfd4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid5 ro 0x00 ssi peripheral id register[15:8] reserved ro 0 ssi peripheral identification 5 (ssiperiphid5) offset 0xfd4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid5
lm3s817 data sheet may 4, 2007 299 preliminary register 12: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid6 ro 0x00 ssi peripheral id register[23:16] reserved ro 0 ssi peripheral identification 6 (ssiperiphid6) offset 0xfd8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid6
synchronous serial interface (ssi) 300 may 4, 2007 preliminary register 13: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid7 ro 0x00 ssi peripheral id register[31:24] reserved ro 0 ssi peripheral identification 7 (ssiperiphid7) offset 0xfdc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid7
lm3s817 data sheet may 4, 2007 301 preliminary register 14: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid0 ro 0x22 ssi peripheral id register[7:0] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 0 (ssiperiphid0) offset 0xfeo 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000100010 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid0
synchronous serial interface (ssi) 302 may 4, 2007 preliminary register 15: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid1 ro 0x00 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 1 (ssiperiphid1) offset 0xfe4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid1
lm3s817 data sheet may 4, 2007 303 preliminary register 16: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid2 ro 0x18 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 2 (ssiperiphid2) offset 0xfe8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000011000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid2
synchronous serial interface (ssi) 304 may 4, 2007 preliminary register 17: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 pid3 ro 0x01 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. reserved ro 0 ssi peripheral identification 3 (ssiperiphid3) offset 0xfec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved pid3
lm3s817 data sheet may 4, 2007 305 preliminary register 18: ssi primecell identification 0 (ssipcellid0), offset 0xff0 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid0 ro 0x0d ssi primecell id register [7:0] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 0 (ssipcellid0) offset 0xff0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000001101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid0
synchronous serial interface (ssi) 306 may 4, 2007 preliminary register 19: ssi primecell identification 1 (ssipcellid1), offset 0xff4 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid1 ro 0xf0 ssi primecell id register [15:8] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 1 (ssipcellid1) offset 0xff4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000011110000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid1
lm3s817 data sheet may 4, 2007 307 preliminary register 20: ssi primecell identification 2 (ssipcellid2), offset 0xff8 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid2 ro 0x05 ssi primecell id register [23:16] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 2 (ssipcellid2) offset 0xff8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000101 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid2
synchronous serial interface (ssi) 308 may 4, 2007 preliminary register 21: ssi primecell identification 3 (ssipcellid3), offset 0xffc the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. bit/field name type reset description 31:8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7:0 cid3 ro 0xb1 ssi primecell id register [31:24] provides software a standard cross-peripheral identification system. reserved ro 0 ssi primecell identification 3 (ssipcellid3) offset 0xffc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000010110001 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved cid3
lm3s817 data sheet may 4, 2007 309 preliminary 14 analog comparator an analog comparator is a perip heral that compares two analog voltages, and provides a logical output that signals the comparison result. the lm3s817 controller provides one analog comparat or that can be configured to drive an output or generate an interrupt or adc event. a comparator can compare a test voltage against any one of these voltages: ? an individual external reference voltage ? a shared single external reference voltage ? a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to sig nal the application via interrupts or triggers to the adc to cause it to start capturing a sample sequ ence. the interrupt generation and adc triggering logic is separate. this means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. 14.1 block diagram figure 14-1. analog comparator module block diagram 14.2 functional description important: it is recommended that the digital-input enable (the gpioden bit in the gpio module) for the analog input pin be disabled to prevent excessive current draw from the i/o pads. the comparator compares the vin- and vin+ inputs to produce an output, vout. as shown in figure 14-2, the input source for vin- is an external input. in addition to an external input, input sources for vin+ can be the +ve input of comparator 0 or an internal reference. voltage ref acrefctl output +ve input (alternate) +ve input interrupt -ve input reference input comparator 0 acstat0 acctl0 c0+ internal bus interrupt c0- c0o
analog comparator 310 may 4, 2007 preliminary figure 14-2. structure of comparator unit a comparator is configured through two status/control registers ( acctl and acstat ). the internal reference is configured through one control register ( acrefctl ). interrupt status and control is configured through three registers ( acmis , acris , and acinten ). the operating modes of the comparators are shown in table 14-1. typically, the comparator output is used internally to generate controller interrupts. it may also be used to drive an external pin or generate an analog-to-digital converter (adc) trigger. important: certain register bit values must be set before using the analog comparators. the proper pad configuration for the comparator input and output pins are described in table 8-1 on page 120. 14.2.1 internal reference programming the structure of the internal reference is shown in figure 14-3. this is controlled by a single configuration register ( acrefctl ). table 14-2 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. table 14-1. comparator 0 operating modes accntl0 comparator 0 asrcp vin- vin+ output interrupt 00 c0- c0+ c0o yes 01 c0- c0+ c0o yes 10 c0- vref c0o yes 11 c0- reserved c0o yes acstat acctl intgen triggen 2 1 0 cinv output -ve input +ve input interrupt internal bus trigger +ve input (alternate) reference input
lm3s817 data sheet may 4, 2007 311 preliminary figure 14-3. comparator inte rnal reference structure 14.3 initialization and configuration the following example shows how to configure analog comparator to read back its output value from an internal register. 1. enable the analog comparator 0 clock by writing a value of 0x00100000 to the rcgc1 register in the system control module. 2. in the gpio module, enable the gpio port/pin associated with c0- as a gpio input. 3. configure the internal voltage reference to 1.65 v by writing the acrefctl register with the value 0x0000030c. 4. configure comparator 0 to use the internal voltage reference and to not invert the output on the c0o pin by writing the acctl0 register with the value of 0x0000040c. table 14-2. internal reference voltage and acrefctl field values acrefctl register output reference voltage based on vref field value en bit value rng bit value en=0 rng=x 0 v (gnd) for any value of vref; however, it is recommended that rng=1 and vref=0 for the least noisy ground reference. en=1 rng=0 total resistance in ladder is 32 r. the range of internal reference in this mode is 0.825?2.37 v. rng=1 total resistance in ladder is 24 r. the range of internal reference for this mode is 0.0?2.0625 v. 8r r r 8r r r ??? ??? 0 decoder 1 15 14 avdd en internal reference vref rng v ref av dd r vref r t --------------- - v ref av dd vref 8 + () v ref 0.825 0.103 vref ? v ref av dd r vref r t --------------- - v ref av dd vref () v ref 0.1375 vref ?
analog comparator 312 may 4, 2007 preliminary 5. delay for some time. 6. read the comparator output value by reading the acstat0 register?s oval value. change the level of the signal input on c0- to see the oval value change. 14.4 register map table 14-3 lists the comparator registers. the of fset listed is a hexadecimal increment to the register?s address, relative to the analog comparator base ad dress of 0x4003c000. 14.5 register descriptions the remainder of this section lists and describes the analog comparator registers, in numerical order by address offset. table 14-3. analog comparator register map offset name reset type description see page 0x00 acmis 0x00000000 r/w1c interrupt status 313 0x04 acris 0x00000000 ro raw interrupt status 314 0x08 acinten 0x00000000 r/w interrupt enable 315 0x10 acrefctl 0x00000000 r/w reference voltage control 316 0x20 acstat0 0x00000000 ro comparator 0 status 317 0x24 acctl0 0x00000000 r/w comparator 0 control 318
lm3s817 data sheet may 4, 2007 313 preliminary register 1: analog comparator masked interrupt status (acmis), offset 0x00 this register provides a summary of the in terrupt status (masked) of the comparator. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 in0 r/1wc 0 comparator 0 masked interrupt status gives the masked interrupt state of this interrupt. write 1 to this field to clear the pending interrupt. reserved ro 0 analog comparator masked interrupt status (acmis) offset 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 in0 ro 0
analog comparator 314 may 4, 2007 preliminary register 2: analog comparator raw interrupt status (acris), offset 0x04 this register provides a summary of the interrupt status (raw) of the comparator. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 in0 ro 0 when set, indicates that an interrupt has been generated by comparator 0. reserved ro 0 analog comparator raw interrupt status (acris) offset 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 in0 ro 0
lm3s817 data sheet may 4, 2007 315 preliminary register 3: analog comparator interrupt enable (acinten), offset 0x08 this register provides the interrupt enable for the comparator. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 in0 r/w 0 when set, enables the controller interrupt from t he comparator 0 output. reserved ro 0 analog comparator interrupt enable (acinten) offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 in0 r/w 0
analog comparator 316 may 4, 2007 preliminary register 4: analog comparator reference voltage control (acrefctl), offset 0x10 this register specifies whether the resistor ladde r is powered on as well as the range and tap. bit/field name type reset description 31:10 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 9enr/w0the en bit specifies whether the resistor ladder is powered on. if 0, the resistor ladder is unpowered. if 1, the resistor ladder is connected to the analog v dd . this bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 8 rng r/w 0 the rng bit specifies the range of th e resistor ladder. if 0, the resistor ladder has a total resist ance of 32 r. if 1, the resistor ladder has a total resistance of 24 r. 7:4 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 3:0 vref r/w 0 the vref bit field specifies the resistor ladder tap that is passed through an analog multiplexer. the voltage corresponding to the tap position is the internal reference voltage available for comparison. see table 14-2 on page 311 for some output reference voltage examples. reserved ro 0 analog comparator reference voltage control (acrefctl) offset 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 rng r/w 0 en r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 vref
lm3s817 data sheet may 4, 2007 317 preliminary register 5: analog comparator status 0 (acstat0), offset 0x20 this register specifies the current output value of that comparator. bit/field name type reset description 31:2 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1ovalro0the oval bit specifies the current output value of the comparator. 0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. reserved ro 0 analog comparator status 0 (acstat0) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved 0 ro 0 oval ro 00 reserved
analog comparator 318 may 4, 2007 preliminary register 6: analog comparator control 0 (acctl0), offset 0x24 this register configures that comparator?s input and output. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11 toen r/w 0 the toen bit enables the adc event transmission to the adc. if 0, the event is suppress ed and not sent to the adc. if 1, the event is transmitted to the adc. 10:9 asrcp r/w 0 the asrcp field specifies the source of input voltage to the vin+ terminal of the comparator. the encodings for this field are as follows: 8 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 7tslvalr/w0the tslval bit specifies the sense value of the input that generates an adc event if in le vel sense mode. if 0, an adc event is generated if the compar ator output is low. otherwise, an adc event is generated if th e comparator output is high. 6:5 tsen r/w 0 the tsen field specifies the sense of the comparator output that generates an adc event. the sense conditioning is as follows: reserved ro 0 analog comparator control 0 (acctl0) offset 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 00000000000000 rororor/wrororororororororororo reserved 0 tslval toen r/w 0 ro 0 r/w 0 r/w 0 asrcp r/w 0 r/w 0 tsen islval r/w 0 r/w 0 r/w 0 isen ro 0 cinv r/w 0 reserved reserved asrcp function 00 pin value 01 pin value of c0+ 10 internal voltage reference 11 reserved tsen function 00 level sense, see tslval 01 falling edge 10 rising edge 11 either edge
lm3s817 data sheet may 4, 2007 319 preliminary 4islvalr/w0the islval bit specifies the sense value of the input that generates an interrupt if in level sense mode. if 0, an interrupt is generated if the comparator output is low. otherwise, an interrupt is generated if the comparator output is high. 3:2 isen r/w 0 the isen field specifies the sense of the comparator output that generates an interrupt. the sense conditioning is as follows: 1cinvr/w0the cinv bit conditionally inverts the output of the comparator. if 0, the output of the comparator is unchanged. if 1, the output of the comparat or is inverted prior to being processed by hardware. 0 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. bit/field name type reset description isen function 00 level sense, see islval 01 falling edge 10 rising edge 11 either edge
pulse width mo dulator (pwm) 320 may 4, 2007 preliminary 15 pulse width modulator (pwm) pulse width modulation (pwm) is a powerful techni que for digitally encoding analog signal levels. high-resolution counters are used to generate a sq uare wave, and the duty cycle of the square wave is modulated to encode an analog signal . typical applications include switching power supplies and motor control. the lm3s817 pwm module consists of pwm generator block and a control block. pwm generator block contains one timer (16-bit down or up/down counter), two comparators, a pwm signal generator, a dead-band generator, and an interrupt selector. the control block determines the polarity of the pwm signals, and whic h signals are passed through to the pins. pwm generator block produces two pwm signals that can either be independent signals (other than being based on the same timer and therefore having the same frequency) or a single pair of complementary signals with dead-band delays insert ed. the output of the pwm generation block managed by the output control block bef ore being passed to the device pins. the lm3s817 pwm module provides a great deal of flexibility. it can generate simple pwm signals, such as those required by a simple charge pump. it can also generate paired pwm signals with dead-band delays, such as those required by a half-h bridge driver. 15.1 block diagram figure 15-1 provides a block diagram of a stellaris pwm module. figure 15-1. pwm module block diagram 15.2 functional description 15.2.1 pwm timer the timer runs in one of two modes: count-down mode or count-up/down mode. in count-down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. in count-up/down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. generally, count-down mode is used for generating left- or right-aligned pwm signals, while the count-up/down mode is used for generating center-aligned pwm signals. the timers output three signals that are used in the pwm generation process: the direction signal (this is always low in count-down mode, but alternates between low and high in count-up/down mode), a single-clock-cycle-width high pulse when the counter is zero, and a single-clock-cycle-width high pulse when the counte r is equal to the load value. note that in count-down mode, the zero pulse is i mmediately followed by the load pulse. 15.2.2 pwm comparators there are two comparators in pwm generator that monitor the value of the counter; when either match the counter, they output a single-clock-cycle-width high pulse. when in count-up/down mode, these comparators match both when coun ting up and when counting down; they are therefore qualified by the counter direction signa l. these qualified pulses are used in the pwm generation process. if either comparator match va lue is greater than the counter load value, then that comparator never outputs a high pulse. figure 15-2 shows the behavior of the counter an d the relationship of these pulses when the counter is in count-down mo de. figure 15-3 shows the behavior of the counter and the relationship of these pulses when the counter is in count-up/down mode.
lm3s817 data sheet may 4, 2007 321 preliminary figure 15-2. pwm count-down mode figure 15-3. pwm count-up/down mode 15.2.3 pwm signal generator the pwm generator takes these pulses (qualified by the direction signal), and generates two pwm signals. in count-down mode, there are four events that can affect the pwm signal: zero, load, match a down, and match b down. in count-up/down mode, there are six events that can affect the pwm signal: zero, lo ad, match a down, match a up, match b down, and match b up. the match a or match b events are ignored when they coincide with the zero or load events. if the match a and match b events coincide, the first signal, pwma , is generated based only on the match a event, and the second signal, pwmb , is generated based only on the match b event. for each event, the effect on each output pwm signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven low, or it can be driven high. these actions can be used to generate a pair of pwm signals of various positions and duty cycles, which do or do not overlap. figure 15-4 shows the use of count-up/down mode to generate a pair of center-aligned, overlapped pwm signals that have different duty cycles. load zero compb compa load zero b a dir adown bdown load zero compb compa load zero b a dir bup aup adown bdown
pulse width mo dulator (pwm) 322 may 4, 2007 preliminary figure 15-4. pwm generation example in count-up/down mode in this example, the first generator is set to dr ive high on match a up, dr ive low on match a down, and ignore the other four events. the second gener ator is set to drive high on match b up, drive low on match b down, and ignore the other four events. changing the value of comparator a changes the duty cycle of the pwma signal, and changing the value of comparator b changes the duty cycle of the pwmb signal. 15.2.4 dead-band generator the two pwm signals produced by the pwm generat or are passed to the dead-band generator. if disabled, the pwm signals simply pass through unmo dified. if enabled, the second pwm signal is lost and two pwm signals are generated based on the first pwm signal. the first output pwm signal is the input signal with the rising edge delayed by a programmable amount. the second output pwm signal is the inversion of the inpu t signal with a programmable delay added between the falling edge of the input signal and the rising edge of this new signal. this is therefore a pair of active high sig nals where one is always high, except for a programmable amount of time at transitions wher e both are low. these signals are therefore suitable for driving a half-h br idge, with the dead-band delays preventing shoot-through current from damaging the power electronics. figure 15-5 shows the effect of the dead-band generator on an input pwm signal. figure 15-5. pwm dead-band generator 15.2.5 interrupt selector the pwm generator also takes the same four (or six) counter events and uses them to generate an interrupt. any of these events or a set of t hese events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. the selection of events allows the interrupt to occur at a specific positi on within the pwm signal. note that interrupts are based on the raw events; delays in the pwm signal edges caused by the dead-band generator are not taken into account. 15.2.6 synchronization methods there is a global reset capability that can synchronously reset any or all of the counters in the pwm generator. load zero compb compa pwmb pwma input pwma pwmb rising edge delay falling edge delay
lm3s817 data sheet may 4, 2007 323 preliminary the counter load values and comparator match values of the pwm generator can be updated in two ways. the first is immediate update mode, wher e a new value is used as soon as the counter reaches zero. by waiting for the counter to reac h zero, a guaranteed behavior is defined, and overly short or overly long output pwm pulses are prevented. the other update method is synchronous, wher e the new value is not used until a global synchronized update signal is asserted, at which point the new value is used as soon as the counter reaches zero. this second mode allows multiple items to be updated simultaneously without odd effects during the update; everything ru ns from the old values until a point at which they all run from the new values. 15.2.7 fault conditions there are two external conditions that affect the pwm block; the signal input on the fault pin and the stalling of the controller by a debugger. there are two mechanisms available to handle such conditions: the output signals can be forced into an inactive state and/or the pwm timers can be stopped. each output signal has a fault bit. if set, a fault input signal causes the corresponding output signal to go into the inactive state. if the inactive state is a safe condition for the signal to be in for an extended period of time, this keeps the output si gnal from driving the outside world in a dangerous manner during the fault condition. a fault cond ition can also generate a controller interrupt. each pwm generator can also be configured to st op counting during a stall condition. the user can select for the co unters to run until they reach zero then stop, or to continue counting and reloading. a stall condition does not generate a controller interrupt. 15.2.8 output c ontrol block with pwm generator block producing two raw pwm signals, the output control block takes care of the final conditioning of the pwm si gnals before they go to the pins. via a single register, the set of pwm signals that are actually enabled to the pins can be modified; this can be used, for example, to perform commutation of a brushless dc moto r with a single register write (and without modifying the individual pwm generators, which ar e modified by the feedback control loop). similarly, fault control can disable any of the pw m signals as well. a final inversion can be applied to any of the pwm signals, making them ac tive low instead of the default active high. 15.3 initialization and configuration the following example shows how to initialize the pwm generator 0 with a 25-khz frequency, and with a 25% duty cycle on the pwm0 pin and a 75% duty cycle on the pwm1 pin. this example assumes the system clock is 20 mhz. 1. enable the pwm clock by writing a value of 0x00100000 to the rcgc0 register in the system control module. 2. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register. 3. configure the run-mode clock configuration (rcc) register in the system control module to use the pwm divide ( usepwmdiv ) and set the divider ( pwmdiv ) to divide by 2 (000). 4. configure the pwm generator for countdown mode with immediate updates to the parameters. ? write the pwm0ctl register with a value of 0x00000000. ? write the pwm0gena register with a value of 0x0000008c. ? write the pwm0genb register with a value of 0x0000080c.
pulse width mo dulator (pwm) 324 may 4, 2007 preliminary 5. set the period. for a 25-khz frequency, the pe riod = 1/25,000, or 40 microseconds. the pwm clock source is 10 mhz; the syste m clock divided by 2. this translates to 400 clock ticks per period. use this value to set the pwm0load register. in count-down mode, set the load field in the pwm0load register to the requested period minus one. ? write the pwm0load register with a value of 0x0000018f. 6. set the pulse width of the pwm0 pin for a 25% duty cycle. ? write the pwm0cmpa register with a value of 0x0000012b. 7. set the pulse width of the pwm1 pin for a 75% duty cycle. ? write the pwm0cmpb register with a value of 0x00000063. 8. start the timers in pwm generator 0. ? write the pwm0ctl register with a value of 0x00000001. 9. enable pwm outputs. ? write the pwmenable register with a value of 0x00000003. 15.4 register map table 15-2 lists the pwm registers. the offset liste d is a hexadecimal increment to the register?s address, relative to the pwm base address of 0x40028000. table 15-1. pwm register map (sheet 1 of 2) offset name reset type description see page pwm module control 0x000 pwmctl 0x00000000 r/w master control of the pwm module 326 0x004 pwmsync 0x00000000 r/w counter synch ronization for the pwm generators 327 0x008 pwmenable 0x00000000 r/w master enable for the pwm output pins 328 0x00c pwminvert 0x00000000 r/w inversion control for the pwm output pins 329 0x010 pwmfault 0x00000000 r/w fault handling for the pwm output pins 330 0x014 pwminten 0x00000000 r/ w interrupt enable 331 0x018 pwmris 0x00000000 ro raw interrupt status 332 0x01c pwmisc 0x00000000 r/w1c inte rrupt status and clear 333 0x020 pwmstatus 0x00000000 ro value of the fault input signal 334 pwm generator 0 0x040 pwm0ctl 0x00000000 r/w master contro l of the pwm0 generator block 335 0x044 pwm0inten 0x00000000 r/ w interrupt enable 336 0x048 pwm0ris 0x00000000 ro raw interrupt status 337 0x04c pwm0isc 0x00000000 r/w1c interrupt status and clear 338 0x050 pwm0load 0x00000000 r/w lo ad value for the counter 339
lm3s817 data sheet may 4, 2007 325 preliminary 15.5 register descriptions the remainder of this section lists and describes the pwm registers, in numerical order by address offset. 0x054 pwm0count 0x00000000 ro current counter value 339 0x058 pwm0cmpa 0x00000000 r/w comparator a value 341 0x05c pwm0cmpb 0x00000000 r/w comparator b value 342 0x060 pwm0gena 0x00000000 r/w c ontrols pwm generator a 343 0x064 pwm0genb 0x00000000 r/w c ontrols pwm generator b 345 0x068 pwm0dbctl 0x00000000 r/w contr ol the dead-band generator 346 0x06c pwm0dbrise 0x00000000 r/w dead-band rising-edge delay count 347 0x070 pwm0dbfall 0x00000000 r/w dead-band falling-edge delay count 348 table 15-1. pwm register map (sheet 2 of 2) offset name reset type description see page
pulse width mo dulator (pwm) 326 may 4, 2007 preliminary register 1: pwm master control (pwmctl), offset 0x000 this register provides master contro l over the pwm generation block. bit/field name type reset description 31: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 globalsync0 r/w 0 setting this bit causes any queued update to a load or comparator register in pwm generator 0 to be applied the next time the corresponding counter becomes zero. this bit automatically clears when the updates have completed; it cannot be cleared by software.
lm3s817 data sheet may 4, 2007 327 preliminary register 2: pwm time base sync (pwmsync), offset 0x004 this register provides a method to perform synchr onization of the counters in the pwm generation blocks. writing a bit in this register to 1 causes the specified counter to reset back to 0; writing multiple bits resets multiple counters simultaneously. the bits auto-clear after the reset has occurred; reading them back as zero indicate s that the synchronization has completed. bit/field name type reset description 31: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 sync0 r/w 0 performs a reset of the pwm generator 0 counter.
pulse width mo dulator (pwm) 328 may 4, 2007 preliminary register 3: pwm output enable (pwmenable), offset 0x008 this register provides a master control of which generated pwm signals are output to device pins. by disabling a pwm output, the generation proc ess can continue (for example when the time bases are synchronized) without driving pwm signals to the pins. when bits in this register are set, the corresponding pwm signal is passed throu gh to the output stage, which is controlled by the pwminvert register. when bits are not set, the pw m signal is replaced by a zero value which is also passed to the output stage. bit/field name type reset description 31: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pwm1en r/w 0 when set, allows the generated pwm1 signal to be passed to the device pin. 0 pwm0en r/w 0 when set, allows the generated pwm0 signal to be passed to the device pin.
lm3s817 data sheet may 4, 2007 329 preliminary register 4: pwm output inve rsion (pwminvert), offset 0x00c this register provides a master control of the po larity of the pwm signals on the device pins. the pwm signals generated by the dead-band block are active high; they can optionally be made active low via this register. disabled pwm channels are also passed through the output inverter (if so configured) so that inactive channels maintain the correct polarity. bit/field name type reset description 31: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 pwm1inv r/w 0 when set, the generated pwm1 signal is inverted. 0 pwm0inv r/w 0 when set, the generated pwm0 signal is inverted.
pulse width mo dulator (pwm) 330 may 4, 2007 preliminary register 5: pwm output fault (pwmfault), offset 0x010 this register controls the behavior of the pwm outp uts in the presence of fault conditions. both the fault input and debug events are considered faul t conditions. on a faul t condition, each pwm signal can either be passed through unmodified or driven low. for outputs that are configured for pass-through, the debug event handling on the corresponding pwm generator also determines if the pwm signal continues to be generated. fault condition control happens before the output inverter, so pwm signals driven low on fault are inverted if the channel is configured for invers ion (therefore, the pin is driven high on a fault condition). bit/field name type reset description 31: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 1 fault1 r/w 0 when set, the pwm1 output signal is driven low on a fault condition. 0 fault0 r/w 0 when set, the pwm0 output signal is driven low on a fault condition.
lm3s817 data sheet may 4, 2007 331 preliminary register 6: pwm interrupt enable (pwminten), offset 0x014 this register controls the global interr upt generation capabilities of the pwm module. the events that can cause an interrupt are the fault input and the individual interrupts from the pwm generator. bit/field name type reset description 31:17 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 16 intfault r/w 0 when 1, an interrupt occurs when the fault input is asserted. 15: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 intpwm0 r/w 0 when 1, an interrupt occurs when the pwm generator 0 block asserts an interrupt.
pulse width mo dulator (pwm) 332 may 4, 2007 preliminary register 7: pwm raw interrupt status (pwmris), offset 0x018 this register provides the curren t set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. the fault interrupt is latched on detection; it must be cleared through the pwm interrupt status and clear (pwmisc) register (see page 333). the pwm generator interrupts simply re flect the status of the pwm generator; they are cleared via the interrupt status register in the pwm generator block. bits set to 1 indicate the events that are active; a zero bit indicates that the event in question is not active.
lm3s817 data sheet may 4, 2007 333 preliminary register 8: pwm interrupt status and clear (pwmisc), offset 0x01c this register provides a summary of the interrupt status of the pwm generator block. a bit set to 1 indicates that the generator block is asserting an interrupt. the individual interrupt status registers must be consulted to determine the reason for the interrupt, and used to clear the interrupt. for the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. bit/field name type reset description 31:17 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 16 intfault r/w1c 0 indicates if the faul t input is asserting an interrupt. 15: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 intpwm0 ro 0 indicates if the pwm gen erator 0 block is asserting an interrupt.
pulse width mo dulator (pwm) 334 may 4, 2007 preliminary register 9: pwm status (pwmstatus), offset 0x020 this register provides the status of the fault input signal. bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 fault ro 0 when set to 1, indicates the fault input is asserted. reserved ro 0 pwm status (pwmstatus) offset 0x020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved fault
lm3s817 data sheet may 4, 2007 335 preliminary register 10: pwm0 control (pwm0ctl), offset 0x040 the register update mode, debug mode, counting mode, and block enable mode are all controlled via . the block produce the pwm signa ls, which can be either two independent pwm signals (from the same counter), or a paired set of pwm signals with dead-band delays added. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 cmpbupd r/w 0 same as cmpaupd but for the comparator b register. 4 cmpaupd r/w 0 the update mode for the comparator a register. if 0, updates to the register are refl ected to the comparator the next time the counter is 0. if 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 326). 3 loadupd r/w 0 the update mode for the l oad register. if 0, updates to the register are reflected to the counter the next time the counter is 0. if 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwm master control (pwmctl) register. 2 debug r/w 0 the behavior of the counter in debug mode. if 0, the counter stops running when it next reaches 0, and continues running again when no longer in debug mode. if 1, the counter always runs. 1 mode r/w 0 the mode for the counter. if 0, the counter counts down from the load value to 0 and then wraps back to the load value (count-down mode). if 1, the counter counts up from 0 to the load value, back down to 0, and then repeats (count-up/down mode). 0 enable r/w 0 master enable for the pwm generation block. if 0, the entire block is disabled and not clocked. if 1, the block is enabled and produces pwm signals. reserved ro 0 pwmn control (pwmnctl) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w cmpbupd reserved enable mode debug loadupd cmpaupd
pulse width mo dulator (pwm) 336 may 4, 2007 preliminary register 11: pwm0 interrupt enable (pwm0inten), offset 0x044 these registers control the interr upt generation capabilities of t he pwm generator. th e events that can cause an interrupt are: ? the counter being equal to the load register ? the counter being equal to zero ? the counter being equal to the comparator a register while counting up ? the counter being equal to the comparator a register while counting down ? the counter being equal to the comparator b register while counting up ? the counter being equal to the comparator b register while counting down any combination of these events can generate either an interrupt. bit/field name type reset description 31: reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 intcmpbd r/w 0 when 1, an interrupt occurs when the counter matches the comparator b value and the counter is counting down. 4 intcmpbu r/w 0 when 1, an interrupt occurs when the counter matches the comparator b value and the counter is counting up. 3 intcmpad r/w 0 when 1, an interrupt occurs when the counter matches the comparator a value and the counter is counting down. 2 intcmpau r/w 0 when 1, an interrupt occurs when the counter matches the comparator a value and the counter is counting up. 1 intcntload r/w 0 when 1, an interrupt occurs when the counter matches the pwmnload register. 0 intcntzero r/w 0 when 1, an interrupt occurs when the counter is 0.
lm3s817 data sheet may 4, 2007 337 preliminary register 12: pwm0 raw interrupt status (pwm0ris), offset 0x048 provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 intcmpbd ro 0 indicates that the coun ter has matched the comparator b value while counting down. 4 intcmpbu ro 0 indicates that the coun ter has matched the comparator b value while counting up. 3 intcmpad ro 0 indicates that the coun ter has matched the comparator a value while counting down. 2 intcmpau ro 0 indicates that the coun ter has matched the comparator a value while counting up. 1 intcntload ro 0 indicates that the counter has matched the pwmnload register. 0 intcntzero ro 0 indicates that the counter has matched 0. reserved ro 0 pwmn raw interrupt status (pwmnris) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro intcmpbd reserved intcntzero intcntload intcmpau intcmpad intcmpbu
pulse width mo dulator (pwm) 338 may 4, 2007 preliminary register 13: pwm0 interrupt status and clear (pwm0isc), offset 0x04c provide the current set of interrupt sources that are asserted to the controller. bits set to 1 indicate the latched events that have occurred; a 0 bit indi cates that the event in question has not occurred. these are r/w1c registers; writing a 1 to a bit po sition clears the corres ponding interrupt reason. bit/field name type reset description 31:6 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 5 intcmpbd r/w1c 0 indicates that the co unter has matched the comparator b value while counting down. 4 intcmpbu r/w1c 0 indicates that the co unter has matched the comparator b value while counting up. 3 intcmpad r/w1c 0 indicates that the co unter has matched the comparator a value while counting down. 2 intcmpau r/w1c 0 indicates that the co unter has matched the comparator a value while counting up. 1 intcntload r/w1c 0 indicates that the counter has matched the pwmnload register. 0 intcntzero r/w1c 0 indicates that the counter has matched 0. reserved ro 0 pwmn interrupt status (pwmnisc) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c intcmpbd reserved intcntzero intcntload intcmpau intcmpad intcmpbu
lm3s817 data sheet may 4, 2007 339 preliminary register 14: pwm0 load (pwm0load), offset 0x050 contain the load value for the pwm counter. ba sed on the counter mode, either this value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero. if the load value update mode is immediate, this value is used the next time the counter reaches zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 326). if this register is re-written before the actual update occurs, the previous value is never used and is lost. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 load r/w 0 the counter load value. ro 0 pwmn load (pwmnload) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved load
pulse width mo dulator (pwm) 340 may 4, 2007 preliminary register 15: pwm0 counter (pwm0count), offset 0x054 contain the current value of the pwm counter. when this value matches the load register, a pulse is output; this can drive the gene ration of a pwm signal (via the pwmngena/pwmngenb registers, see page 343 and 345) or drive an interrupt (via the pwmninten register, see page 336). a pulse with the same capabilities is generated when this value is zero. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 count ro 0 the current value of the counter. ro 0 pwmn counter (pwmncount) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro reserved count
lm3s817 data sheet may 4, 2007 341 preliminary register 16: pwm0 compare a (pwm0cmpa), offset 0x058 contain a value to be compared against the counter. when this value matches the counter, a pulse is output; this can drive the generation of a pwm signal (via the pwmngena/pwmngenb registers) or drive an interrupt (via the pwmninten register). if the value of this register is greater than the pwmnload register (see page 339), then no pulse is ever output. for comparator a, if the update mode is immediate (based on the cmpaupd bit in the pwmnctl register), then this 16-bit compa value is used the next time the counter reaches zero. if the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 326). if this register is rewritten before th e actual update occurs, the previous value is never used and is lost. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 compa r/w 0 the value to be compared against the counter. ro 0 pwmn compare a (pwmncmpa) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved compa
pulse width mo dulator (pwm) 342 may 4, 2007 preliminary register 17: pwm0 compare b (pwm0cmpb), offset 0x05c contain a value to be compared against the counter. when this value matches the counter, a pulse is output; this can drive the generation of a pwm signal (via the pwmngena/pwmngenb registers) or drive an interrupt (via the pwmninten register). if the value of this register is greater than the pwmnload register, then no pulse is ever output. for comparator b, if the update mode is immediate (based on the cmpbupd bit in the pwmnctl register), then this 16-bit compb value is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 326). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. bit/field name type reset description 31:16 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 15:0 compb r/w 0 the value to be compared against the counter. ro 0 pwmn compare b (pwmncmpb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w 0 reset type 000000000000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved compb
lm3s817 data sheet may 4, 2007 343 preliminary register 18: pwm0 generator a control (pwm0gena), offset 0x060 control the generation of the pwmna signal based on the load and zero output pulses from the counter, as well as the compare a and compare b pulses from the comparators. when the counter is running in count-down mode, on ly four of these events occur; when running in count-up/down mode, all six occur. these events provide great flexibility in the positioning and duty cycle of the pwm signal that is produced. the pwm0gena register controls generation of the pwm0a signal. each field can take on one of the values defined in table 15-2, which defines the effect of the event on the output signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare a action is taken and the compare b action is ignored. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11:10 actcmpbd r/w 0 the action to be taken when the counter matches comparator b while counting down. 9:8 actcmpbu r/w 0 the action to be taken when the counter matches comparator b while counting up. occurs only when the mode bit in the pwmnctl register (see page 335) is set to 1. 7:6 actcmpad r/w 0 the action to be taken when the counter matches comparator a while counting down. 5:4 actcmpau r/w 0 the action to be taken when the counter matches comparator a while counting up.occurs only when the mode bit in the pwmnctl register is set to 1. 3:2 actload r/w 0 the action to be taken when the counter matches the load value. 1:0 actzero r/w 0 the action to be taken when the counter is zero. reserved ro 0 pwmn generator a control (pwmngena) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved actcmpad actcmpau actload actzero actcmpbu actcmpbd
pulse width mo dulator (pwm) 344 may 4, 2007 preliminary table 15-2. pwm generator action encodings value description 00 do nothing. 01 invert the output signal. 10 set the output signal to 0. 11 set the output signal to 1.
lm3s817 data sheet may 4, 2007 345 preliminary register 19: pwm0 generator b control (pwm0genb), offset 0x064 control the generation of the pwmnb signal based on the load and zero output pulses from the counter, as well as the compare a and compare b pulses from the comparators. when the counter is running in down mode, only four of these events occur; when running in up/down mode, all six occur. these events provide grea t flexibility in the positioning and duty cycle of the pwm signal that is produced. the pwm0genb register controls generation of the pwm0b signal. each field can take on one of the values defined in table 15-2 on page 344, which defines the effect of the event on the output signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare b action is taken and the compare a action is ignored. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11:10 actcmpbd r/w 0 the action to be taken when the counter matches comparator b while counting down. 9:8 actcmpbu r/w 0 the action to be taken when the counter matches comparator b while counting up. occurs only when the mode bit in the pwmnctl register (see page 335) is set to 1. 7:6 actcmpad r/w 0 the action to be taken when the counter matches comparator a while counting down. 5:4 actcmpau r/w 0 the action to be taken when the counter matches comparator a while counting up. occurs only when the mode bit in the pwmnctl register is set to 1. 3:2 actload r/w 0 the action to be taken when the counter matches the load value. 1:0 actzero r/w 0 the action to be taken when the counter is 0. reserved ro 0 pwmn generator b control (pwmngenb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved actcmpad actcmpau actload actzero actcmpbu actcmpbd
pulse width mo dulator (pwm) 346 may 4, 2007 preliminary register 20: pwm0 dead-band control (pwm0dbctl), offset 0x068 the pwm0dbctl register controls the dead-ba nd generator, which produces the pwm0 and pwm1 signals based on the pwm0a and pwm0b signals. when disabled, the pwm0a signal passes through to the pwm0 signal and the pwm0b signal passes through to the pwm1 signal. when enabled, the pwm0b signal is ignored; the pwm0 signal is generated by delayi ng the rising edge(s) of the pwm0a signal by the value in the pwm0dbrise register (see page 347), and the pwm1 signal is generated by delaying t he falling edge(s) of the pwm0a signal by the value in the pwm0dbfall register (see page 348). bit/field name type reset description 31:1 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 0 enable r/w 0 when set, the dead-band generator inserts dead bands into the output signals; when clear, it simply passes the pwm signals through. reserved ro 0 pwmn dead-band control (pwmndbctl) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w reserved enable
lm3s817 data sheet may 4, 2007 347 preliminary register 21: pwm0 dead-band rising-e dge delay (pwm0dbri se), offset 0x06c the pwm0dbrise register contains the number of clock ticks to delay the rising edge of the pwm0a signal when generating the pwm0 signal. if the dead-band generator is disabled through the pwmndbctl register, the pwm0dbrise register is ignored. if the value of this register is larger than the width of a high pulse on the input pwm signal, the rising-edge delay consumes the entire high time of the signal, resulting in no high time on the output. care must be taken to ensure that the input high time always exceeds the rising-edge delay. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11:0 risedelay r/w 0 the number of clock ticks to delay the rising edge. reserved ro 0 pwmn dead-band rising-edge delay (pwmndbrise) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved risedelay
pulse width mo dulator (pwm) 348 may 4, 2007 preliminary register 22: pwm0 dead-band falling-edge-delay (pwm0dbfall), offset 0x070 the pwm0dbfall register contains the number of cloc k ticks to delay the falling edge of the pwm0a signal when generating the pwm1 signal. if the dead-band generator is disabled, this register is ignored. if the value of this register is larger than the width of a low pulse on the input pwm signal, the falling-edge delay consumes the entire low time of the signal, resu lting in no low time on the output. care must be taken to ensure that the input low time always exceeds the falling-edge delay. bit/field name type reset description 31:12 reserved ro 0 reserved bits return an indeterminate value, and should never be changed. 11:0 falldelay r/w 0 the number of cl ock ticks to delay the fallin g edge. reserved ro 0 pwmn dead-band falling-edge-delay register (pwmndbfall) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset type 000000000000000 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro 0 reset type 000000000000000 ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reserved falldelay
lm3s817 data sheet may 4, 2007 349 preliminary 16 pin diagram figure 16-1 shows the pin diagram and pin-to-signal-name mapping. figure 16-1. pin connection diagram 1 36 13 48 2 14 5 6 3 4 7 8 11 9 10 47 15 46 16 45 17 44 18 43 19 42 20 41 21 40 22 39 23 38 34 33 35 32 30 29 31 28 26 27 12 25 24 37 rst ldo vdd gnd osc0 osc1 pa0/u0rx pa1/u0tx pa2/ssiclk pa3/ssifss vdd gnd pb7/trst pa4/ssirx pc0/tck/swclk pa5/ssitx pc1/tms/swdio vdd pc2/tdi vdd gnd gnd pc3/tdo/swo adc0 pe1/pwm5 pc5/ccp1 adc4 adc1 pc4/ccp5 adc2 adc3 pc7/ccp4 adc5 pd5/ccp2 pd4/ccp0 pb4/c0- pb5/c0o pb6/c0+ pb3/fault pb2 pe0/pwm4 pb1/pwm3 pb0/pwm2 pd3/u1tx pd1/pwm1 pd2/u1rx pc6/ccp3 lm3s817 pd0/pwm0
signal tables 350 may 4, 2007 preliminary 17 signal tables the following tables list the signals available for ea ch pin. functionality is enabled by software with the gpioafsel register (see page 132). important: all multiplexed pins are gpios by default, with the exception of the five jtag pins ( pb7 and pc[3:0] ) which default to the jtag functionality. shows the pin-to-signal-name mapping, including func tional characteristics of the signals. lists the signals in alphabetical order by signal name. gr oups the signals by functionality, except for gpios. lists the gpio pins and their alternate functionality. table 17-1. signals by pin number (sheet 1 of 3) pin number pin name pin type buffer type description 1 adc0 i analog analog-to-digital converter input 0. 2 adc1 i analog analog-to-digital converter input 1. 3 adc2 i analog analog-to-digital converter input 2. 4 adc3 i analog analog-to-digital converter input 3. 5rst i ttl system reset input. 6 ldo - power the low drop-out regulator ou tput voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. 7 vdd - power positive supply for logic and i/o pins. 8 gnd - power ground reference for logic and i/o pins. 9 osc0 i analog oscillator crystal input or an external clock reference input. 10 osc1 o analog oscillator crystal output. 11 pc7 i/o ttl gpio port c bit 7. ccp4 i/o ttl timer 2 capture input, comp are output, or pwm output channel 4. 12 pc6 i/o ttl gpio port c bit 6. ccp3 i/o ttl timer 1 capture input, comp are output, or pwm output channel 3. 13 pc5 i/o ttl gpio port c bit 5. ccp1 i/o ttl timer 0 capture input, comp are output, or pwm output channel 1. 14 pc4 i/o ttl gpio port c bit 4. ccp5 i/o ttl timer 2 capture input, comp are output, or pwm output channel 5. 15 vdd - power positive supply for logic and i/o pins. 16 gnd - power ground reference for logic and i/o pins. 17 pa0 i/o ttl gpio port a bit 0. u0rx i ttl uart0 receive data input.
lm3s817 data sheet may 4, 2007 351 preliminary 18 pa1 i/o ttl gpio port a bit 1. u0tx o ttl uart0 transmit data output. 19 pa2 i/o ttl gpio port a bit 2. ssiclk i/o ttl ssi clock reference (input when in slave mode and output in master mode). 20 pa3 i/o ttl gpio port a bit 3. ssifss i/o ttl ssi frame enable (input for an ssi slave device and output for an ssi master device). 21 pa4 i/o ttl gpio port a bit 4. ssirx i ttl ssi receive data input. 22 pa5 i/o ttl gpio port a bit 5. ssitx o ttl ssi transmit data output. 23 vdd - power positive supply for logic and i/o pins. 24 gnd - power ground reference for logic and i/o pins. 25 pd0 i/o ttl gpio port d bit 0. pwm0 o ttl pulse width modulator channel 0 output. 26 pd1 i/o ttl gpio port d bit 1. pwm1 o ttl pulse width modulator channel 1 output. 27 pd2 i/o ttl gpio port d bit 2. u1rx i ttl uart1 receive data input. 28 pd3 i/o ttl gpio port d bit 3. u1tx o ttl uart1 transmit data output. 29 pb0 i/o ttl gpio port b bit 0. pwm2 o ttl pulse width modulator channel 2 output. 30 pb1 i/o ttl gpio port b bit 1. pwm3 o ttl pulse width modulator channel 3 output. 31 gnd - power ground reference for logic and i/o pins. 32 vdd - power positive supply for logic and i/o pins. 33 pb2 i/o ttl gpio port b bit 2. 34 pb3 i/o ttl gpio port b bit 3. fault i ttl motion control 0 fault. table 17-1. signals by pin number (sheet 2 of 3) pin number pin name pin type buffer type description
signal tables 352 may 4, 2007 preliminary 35 pe0 i/o ttl gpio port e bit 0. pwm4 o ttl pulse width modulator channel 4 output. 36 pe1 i/o ttl gpio port e bit 1. pwm5 o ttl pulse width modulator channel 5 output. 37 pc3 i/o ttl gpio port c bit 3. tdo o ttl jtag scan test data output. swo o ttl serial-wire output. 38 pc2 i/o ttl gpio port c bit 2. tdi i ttl jtag scan test data input. 39 pc1 i/o ttl gpio port c bit 1. tms i ttl jtag scan test mode select input. swdio i/o ttl serial-wir e debug input/output. 40 pc0 i/o ttl gpio port c bit 0. tck i ttl jtag scan test clock reference input. swclk i ttl serial wire clock reference input. 41 pb7 i/o ttl gpio port b bit 7. trst i ttl jtag scan test reset input. 42 pb6 i/o ttl gpio port b bit 6. c0+ i analog analog comparator 0 positive-reference input. 43 pb5 i/o ttl gpio port b bit 5. c0o o ttl analog comparator 0 output. 44 pb4 i/o ttl gpio port b bit 4. c0? i analog analog comparator 0 negative-reference input. 45 pd4 i/o ttl gpio port d bit 4. ccp0 i/o ttl timer 0 capture input, comp are output, or pwm output channel 0. 46 pd5 i/o ttl gpio port d bit 5. ccp2 i/o ttl timer 1 capture input, comp are output, or pwm output channel 2. 47 adc5 i analog analog-to-digital converter input 5. 48 adc4 i analog analog-to-digital converter input 4. table 17-1. signals by pin number (sheet 3 of 3) pin number pin name pin type buffer type description
lm3s817 data sheet may 4, 2007 353 preliminary table 17-2. signals by signal name (sheet 1 of 3) pin name pin number pin type buffer type description adc0 1 i analog analog-to-digital converter input 0. adc1 2 i analog analog-to-digital converter input 1. adc2 3 i analog analog-to-digital converter input 2. adc3 4 i analog analog-to-digital converter input 3. adc4 48 i analog analog-to-digital converter input 4. adc5 47 i analog analog-to-digital converter input 5. c0+ 42 i analog analog comparator 0 positive-reference input. c0? 44 i analog analog comparator 0 negative-reference input. c0o 43 o ttl analog comparator 0 output. ccp0 45 i/o ttl timer 0 capture input, comp are output, or pwm output channel 0. ccp1 13 i/o ttl timer 0 capture input, comp are output, or pwm output channel 1. ccp2 46 i/o ttl timer 1 capture input, comp are output, or pwm output channel 2. ccp3 12 i/o ttl timer 1 capture input, comp are output, or pwm output channel 3. ccp4 11 i/o ttl timer 2 capture input, comp are output, or pwm output channel 4. ccp5 14 i/o ttl timer 2 capture input, comp are output, or pwm output channel 5. fault 34 i ttl motion control 0 fault. gnd 8 - power ground reference for logic and i/o pins. gnd 16 - power ground reference for logic and i/o pins. gnd 24 - power ground reference for logic and i/o pins. gnd 31 - power ground reference for logic and i/o pins. ldo 6 - power the low drop-out regulator ou tput voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. osc0 9 i analog oscillator crystal input or an external clock reference input. osc1 10 o analog oscillator crystal output. pa0 17 i/o ttl gpio port a bit 0. pa1 18 i/o ttl gpio port a bit 1. pa2 19 i/o ttl gpio port a bit 2. pa3 20 i/o ttl gpio port a bit 3. pa4 21 i/o ttl gpio port a bit 4. pa5 22 i/o ttl gpio port a bit 5. pb0 29 i/o ttl gpio port b bit 0.
signal tables 354 may 4, 2007 preliminary pb1 30 i/o ttl gpio port b bit 1. pb2 33 i/o ttl gpio port b bit 2. pb3 34 i/o ttl gpio port b bit 3. pb4 44 i/o ttl gpio port b bit 4. pb5 43 i/o ttl gpio port b bit 5. pb6 42 i/o ttl gpio port b bit 6. pb7 41 i/o ttl gpio port b bit 7. pc0 40 i/o ttl gpio port c bit 0. pc1 39 i/o ttl gpio port c bit 1. pc2 38 i/o ttl gpio port c bit 2. pc3 37 i/o ttl gpio port c bit 3. pc4 14 i/o ttl gpio port c bit 4. pc5 13 i/o ttl gpio port c bit 5. pc6 12 i/o ttl gpio port c bit 6. pc7 11 i/o ttl gpio port c bit 7. pd0 25 i/o ttl gpio port d bit 0. pd1 26 i/o ttl gpio port d bit 1. pd2 27 i/o ttl gpio port d bit 2. pd3 28 i/o ttl gpio port d bit 3. pd4 45 i/o ttl gpio port d bit 4. pd5 46 i/o ttl gpio port d bit 5. pe0 35 i/o ttl gpio port e bit 0. pe1 36 i/o ttl gpio port e bit 1. pwm0 25 o ttl pulse width modulator channel 0 output. pwm1 26 o ttl pulse width modulator channel 1 output. pwm2 29 o ttl pulse width modulator channel 2 output. pwm3 30 o ttl pulse width modulator channel 3 output. pwm4 35 o ttl pulse width modulator channel 4 output. pwm5 36 o ttl pulse width modulator channel 5 output. rst 5 i ttl system reset input. table 17-2. signals by signal name (sheet 2 of 3) pin name pin number pin type buffer type description
lm3s817 data sheet may 4, 2007 355 preliminary ssiclk 19 i/o ttl ssi clock reference (input when in slave mode and output in master mode). ssifss 20 i/o ttl ssi frame enable (input for an ssi slave device and output for an ssi master device). ssirx 21 i ttl ssi receive data input. ssitx 22 o ttl ssi transmit data output. swclk 40 i ttl serial wire clock reference input. swdio 39 i/o ttl serial- wire debug input/output. swo 37 o ttl serial-wire output. tck 40 i ttl jtag scan test clock reference input. tdi 38 i ttl jtag scan test data input. tdo 37 o ttl jtag scan test data output. tms 39 i ttl jtag scan test mode select input. trst 41 i ttl jtag scan test reset input. u0rx 17 i ttl uart0 receive data input. u0tx 18 o ttl uart0 transmit data output. u1rx 27 i ttl uart1 receive data input. u1tx 28 o ttl uart1 transmit data output. vdd 7 - power positive supply for logic and i/o pins. vdd 15 - power positive supply for logic and i/o pins. vdd 23 - power positive supply for logic and i/o pins. vdd 32 - power positive supply for logic and i/o pins. table 17-3. signals by function, except for gpio (sheet 1 of 3) function pin name pin number pin type buffer type description adc adc0 1 i analog analog-to-digital converter input 0. adc1 2 i analog analog-to-digital converter input 1. adc2 3 i analog analog-to-digital converter input 2. adc3 4 i analog analog-to-digital converter input 3. adc4 48 i analog analog-to-digital converter input 4. adc5 47 i analog analog-to-digital converter input 5. table 17-2. signals by signal name (sheet 3 of 3) pin name pin number pin type buffer type description
signal tables 356 may 4, 2007 preliminary analog comparators c0+ 42 i analog analog comparator 0 positive-reference input. c0? 44 i analog analog comparator 0 negative-reference input. c0o 43 o ttl analog comparator 0 output. general-purpose timers ccp0 45 i/o ttl timer 0 capture input, compare output, or pwm output channel 0. ccp1 13 i/o ttl timer 0 capture input, compare output, or pwm output channel 1. ccp2 46 i/o ttl timer 1 capture input, compare output, or pwm output channel 2. ccp3 12 i/o ttl timer 1 capture input, compare output, or pwm output channel 3. ccp4 11 i/o ttl timer 2 capture input, compare output, or pwm output channel 4. ccp5 14 i/o ttl timer 2 capture input, compare output, or pwm output channel 5. jtag/swd/swo swclk 40 i ttl serial-wire clock reference input. swdio 39 i/o ttl serial- wire debug input/output. swo 37 o ttl serial-wire output. tck 40 i ttl jtag scan test clock reference input. tdi 38 i ttl jtag scan test data input. tdo 37 o ttl jtag scan test data output. tms 39 i ttl jtag scan test mode select input. trst 41 i ttl jtag scan test reset input. table 17-3. signals by function, except for gpio (sheet 2 of 3) function pin name pin number pin type buffer type description
lm3s817 data sheet may 4, 2007 357 preliminary power gnd 8 - power ground reference for logic and i/o pins. gnd 16 - power ground reference for logic and i/o pins. gnd 24 - power ground reference for logic and i/o pins. gnd 31 - power ground reference for logic and i/o pins. ldo 6 - power the low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater. vdd 7 - power positive supply for logic and i/o pins. vdd 15 - power positive supply for logic and i/o pins. vdd 23 - power positive supply for logic and i/o pins. vdd 32 - power positive supply for logic and i/o pins. pwm pwm0 25 o ttl pulse width modulator channel 0 output. pwm1 26 o ttl pulse width modulator channel 1 output. pwm2 29 o ttl pulse width modulator channel 2 output. pwm3 30 o ttl pulse width modulator channel 3 output. pwm4 35 o ttl pulse width modulator channel 4 output. pwm5 36 o ttl pulse width modulator channel 5 output. ssi ssiclk 19 i/o ttl ssi clock reference (input when in slave mode and output in master mode). ssifss 20 i/o ttl ssi frame enable (input for an ssi slave device and output for an ssi master device). ssirx 21 i ttl ssi receive data input. ssitx 22 o ttl ssi transmit data output. system control & clocks osc0 9 i analog oscillator crystal input or an external clock reference input. osc1 10 o analog oscillator crystal output. rst 5 i ttl system reset input. uart u0rx 17 i ttl uart0 receive data input. u0tx 18 o ttl uart0 transmit data output. u1rx 27 i ttl uart1 receive data input. u1tx 28 o ttl uart1 transmit data output. table 17-3. signals by function, except for gpio (sheet 3 of 3) function pin name pin number pin type buffer type description
signal tables 358 may 4, 2007 preliminary table 17-4. gpio pins and alternate functions (sheet 1 of 2) gpio pin pin number multiplexed function multiplexed function pa0 17 u0rx pa1 18 u0tx pa2 19 ssiclk pa3 20 ssifss pa4 21 ssirx pa5 22 ssitx pb0 29 pwm2 pb1 30 pwm3 pb2 33 pb3 34 fault pb4 44 c0- pb5 43 c0o pb6 42 c0+ pb7 41 trst pc0 40 tck swclk pc1 39 tms swdio pc2 38 tdi pc3 37 tdo swo pc4 14 ccp5 pc5 13 ccp1 pc6 12 ccp3 pc7 11 ccp4 pd0 25 pwm0 pd1 26 pwm1 pd2 27 u1rx pd3 28 u1tx pd4 45 ccp0 pd5 46 ccp2
lm3s817 data sheet may 4, 2007 359 preliminary pd6 47 adc5 pd7 48 adc4 pe0 35 pwm4 pe1 36 pwm5 pe2 4 adc3 pe3 3 adc2 pe4 2 adc1 pe5 1 adc0 table 17-4. gpio pins and alternate functions (sheet 2 of 2) gpio pin pin number multiplexed function multiplexed function
operating characteristics 360 may 4, 2007 preliminary 18 operating characteristics table 18-1. temperature characteristics characteristic symbol value unit operating temperature range a a. maximum storage temperature is 150c. t a -40 to +85 for industrial c table 18-2. thermal characteristics characteristic symbol value unit thermal resistance (junction to ambient) a a. junction to ambient thermal resistance ja numbers are determined by a package simulator. ja 76 c/w average junction temperature b b. power dissipation is a function of temperature. t j t a + (p avg ? ja ) c maximum junction temperature t jmax 115 c c. t jmax calculation is based on power consumpt ion values and conditions as specified in ?power specifications? on page 363 of the data sheet. c
lm3s817 data sheet may 4, 2007 361 preliminary 19 electrical characteristics 19.1 dc characteristics 19.1.1 maximum ratings the maximum ratings are the limits to which t he device can be subjected without permanently damaging the device. note: the device is not guaranteed to oper ate properly at the maximum ratings. important: this device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. reliability of oper ation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either gnd or v dd ). 19.1.2 recommended dc operating conditions table 19-1. maximum ratings characteristic a a. voltages are measured with respect to gnd. symbol value unit supply voltage range (v dd )v dd 0.0 to +3.6 v input voltage v in -0.3 to 5.5 v maximum current for pins, excluding pins operating as gpios i100 ma maximum current for gpio pins i 100 ma table 19-2. recommended dc operating conditions parameter parameter name min nom max unit v dd supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 2.0 - 5.0 v v il low-level input voltage -0.3 - 1.3 v v sih high-level input voltage for schmitt trigger inputs 0.8 * v dd -v dd v v sil low-level input voltage for schmitt trigger inputs 0 - 0.2 * v dd v v oh high-level output voltage 2.4 - - v v ol low-level output voltage - - 0.4 v
electrical characteristics 362 may 4, 2007 preliminary 19.1.3 on-chip low dr op-out (ldo) regulat or characteristics i oh high-level source current, v oh =2.4 v 2-ma drive 2.0 - - ma 4-ma drive 4.0 - - ma 8-ma drive 8.0 - - ma i ol low-level sink current, v ol =0.4 v 2-ma drive 2.0 - - ma 4-ma drive 4.0 - - ma 8-ma drive 8.0 - - ma table 19-3. ldo regulator characteristics parameter parameter name min nom max unit v ldoout programmable internal (logic) power supply output value 2.25 - 2.75 v output voltage accuracy - 2% - % t pon power-on time - - 100 s t on time on - - 200 s t off time off - - 100 s v step step programming incremental voltage - 50 - mv c ldo external filter capacitor size for internal power supply -1-f table 19-2. recommended dc operating conditions (continued) parameter parameter name min nom max unit
lm3s817 data sheet may 4, 2007 363 preliminary 19.1.4 power specifications the power measurements specified in table 19-4 are run on the core processor using sram with the following specifications: ? v dd = 3.3 v ? temperature = 25 c table 19-4. power specifications parameter parameter name conditions nom max unit i dd_run run mode 1 (flash loop) ldo = 2.50 v code = while(1){} executed in flash peripherals = all clock-gated on system clock = 50 mhz (with pll) 95 110 ma run mode 2 (flash loop) ldo = 2.50 v code = while(1){} executed in flash peripherals = all clock-gated off system clock = 50 mhz (with pll) 60 75 ma run mode 1 (sram loop) ldo = 2.50 v code = while(1){} executed in sram peripherals = all clock-gated on system clock = 50 mhz (with pll) 85 95 ma run mode 2 (sram loop) ldo = 2.50 v code = while(1){} executed in sram peripherals = all clock-gated off system clock = 50 mhz (with pll) 50 60 ma i dd_sleep sleep mode ldo = 2.50 v peripherals = all clock-gated off system clock = 50 mhz (with pll) 19 22 ma i dd_deepsleep deep-sleep mode ldo = 2.25 v peripherals = all clock-gated off system clock = mosc/16 950 1150 a
electrical characteristics 364 may 4, 2007 preliminary 19.1.5 flash memory characteristics 19.2 ac characteristics 19.2.1 load conditions unless otherwise specified, the following conditions are true for all timing measurements. timing measurements are for 4-ma drive strength. figure 19-1. load conditions 19.2.2 clocks table 19-5. flash memory characteristics parameter parameter name min nom max unit pe cyc number of guaranteed program/erase cycles a before failure a. a program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 10,000 - - cycles t ret data retention at average operating temperature of 85c 10 - - years t prog word program time 20 - - s t erase page erase time 20 - - ms t me mass erase time 200 - - ms table 19-6. phase locked loop (pll) characteristics parameter parameter name min nom max unit f ref_crystal crystal reference a a. the exact value is determined by the crystal value programmed into the xtal field of the run-mode clock configuration (rcc) register (see page 84). 3.579545 - 8.192 mhz f ref_ext external clock reference a 3.579545 - 8.192 mhz f pll pll frequency b b. pll frequency is automatically calculated by the hardware based on the xtal field of the rcc register. -200-mhz t ready pll lock time - - 0.5 ms c l = 50 pf gnd pin
lm3s817 data sheet may 4, 2007 365 preliminary 19.2.3 analog-to-digital converter table 19-7. clock characteristics parameter parameter name min nom max unit f iosc internal oscillator frequency 71522mhz f mosc main oscillator frequency 1 - 8 mhz t mosc_per main oscillator period 125 - 1000 ns f ref_crystal_bypass crystal reference using the main oscillator (pll in bypass mode) a a. the adc must be clocked from the pll or directly fr om a 14-mhz to 18-mhz clock source in order to operate properly. 1-8mhz f ref_ext_bypass external clock reference (pll in bypass mode) a 0-50mhz f system_clock system clock 0 - 50 mhz table 19-8. adc characteristics parameter parameter name min nom max unit v adcin maximum single-ended, full-scale analog input voltage --3.0v minimum single-e nded, full-scale analog input voltage --0v maximum differential, full-scale analog input voltage --1.5v minimum differential, full-scale analog input voltage ---1.5v c adcin equivalent input capacitance - 1 - pf n resolution - 10 - bits f adc adc internal clock frequency 14 16 18 mhz t adcconv conversion time - - 16 t adc cycles a a. t adc = 1/f adc clock f adcconv conversion rate 875 1000 1125 k samples/s inl integral nonlinearity - - 1 lsb dnl differential nonlinearity - - 1 lsb off offset - - +2 lsb gain gain - - 2 lsb
electrical characteristics 366 may 4, 2007 preliminary 19.2.4 analog comparator 19.2.5 synchronous serial interface (ssi) table 19-9. analog comparator characteristics parameter parameter name min nom max unit v os input offset voltage - 10 25 mv v cm input common mode voltage range 0 - v dd -1.5 v c mrr common mode rejection ratio 50 - - db t rt response time - - 1 s t mc comparator mode change to output valid - - 10 s table 19-10. analog comparator voltage reference characteristics parameter parameter name min nom max unit r hr resolution high range - v dd /32 - lsb r lr resolution low range - v dd /24 - lsb a hr absolute accuracy high range - - 1/2 lsb a lr absolute accuracy low range - - 1/4 lsb table 19-11. ssi characteristics parameter no. parameter parameter name min nom max unit s1 t clk_per ssiclk cycle time 2 - 65024 system clocks s2 t clk_high ssiclk high time - 1/2 - t clk_per s3 t clk_low ssiclk low time - 1/2 - t clk_per s4 t clkrf ssiclk rise/fall time - 7.4 26 ns s5 t dmd data from master valid delay time 0 - 20 ns s6 t dms data from master setup time 20 - - ns s7 t dmh data from master hold time 40 - - ns s8 t dss data from slave setup time 20 - - ns s9 t dsh data from slave hold time 40 - - ns
lm3s817 data sheet may 4, 2007 367 preliminary figure 19-2. ssi timing for ti frame format (frf=01), single transfer timing measurement figure 19-3. ssi timing for microwire frame format (frf=10), single transfer figure 19-4. ssi timing for spi frame format (frf=00), with sph=1 ssiclk ssifss ssitx ssirx msb lsb s2 s3 s1 s4 4 to 16 bits 0 ssiclk ssifss ssitx ssirx msb lsb msb lsb s2 s3 s1 8-bit control 4 to 16 bits output data ssiclk (spo=1) ssitx (master) ssirx (slave) lsb ssiclk (spo=0) s2 s1 s4 ssifss lsb s3 msb s5 s6 s7 s9 s8 msb
electrical characteristics 368 may 4, 2007 preliminary 19.2.6 jtag and boundary scan table 19-12. jtag characteristics parameter no. parameter parameter name min nom max unit j1 f tck tck operational clock frequency 0 - 10 mhz j2 t tck tck operational clock period 100 - - ns j3 t tck_low tck clock low time - ? t tck -ns j4 t tck_high tck clock high time - ? t tck -ns j5 t tck_r tck rise time 0 - 10 ns j6 t tck_f tck fall time 0 - 10 ns j7 t tms_su tms setup time to tck rise 20 - - ns j8 t tms_hld tms hold time from tck rise 20 - - ns j9 t tdi_su tdi setup time to tck rise 25 - - ns j10 t tdi_hld tdi hold time from tck rise 25 - - ns j11 t tdo_zdv tck fall to data valid from high-z 2-ma drive - 23 35 ns 4-ma drive 15 26 ns 8-ma drive 14 25 ns 8-ma drive with slew rate control 18 29 ns j12 t tdo_dv tck fall to data valid from data valid 2-ma drive - 21 35 ns 4-ma drive 14 25 ns 8-ma drive 13 24 ns 8-ma drive with slew rate control 18 28 ns j13 t tdo_dvz tck fall to high-z from data valid 2-ma drive - 9 11 ns 4-ma drive 7 9 ns 8-ma drive 6 8 ns 8-ma drive with slew rate control 7 9 ns j14 t trst trst assertion time 100 - - ns j15 t trst_su trst setup time to tck rise 10 - - ns
lm3s817 data sheet may 4, 2007 369 preliminary figure 19-5. jtag test clock input timing figure 19-6. jtag test access port (tap) timing figure 19-7. jtag trst timing tck j6 j5 j3 j4 j2 tdo output valid tck tdo output valid j12 tdo tdi tms tdi input valid tdi input valid j13 j9 j10 tms input valid j9 j10 tms input valid j11 j7 j8 j8 j7 tck j14 j15 trst
electrical characteristics 370 may 4, 2007 preliminary 19.2.7 general-purpose i/o 19.2.8 reset table 19-13. gpio characteristics a a. all gpios are 5 v-tolerant. parameter parameter name condition min nom max unit t gpior gpo rise time (from 20% to 80% of v dd ) 2-ma drive - 17 26 ns 4-ma drive 9 13 ns 8-ma drive 6 9 ns 8-ma drive with slew rate control 10 12 ns t gpiof gpo fall time (from 80% to 20% of v dd ) 2-ma drive - 17 25 ns 4-ma drive 8 12 ns 8-ma drive 6 10 ns 8-ma drive with slew rate control 11 13 ns table 19-14. reset characteristics parameter no. parameter parameter name min nom max unit r1 v th reset threshold - 2.0 - v r2 v bth brown-out threshold 2.85 2.9 2.95 v r3 t por power-on reset timeout - 10 - ms r4 t bor brown-out timeout - 500 - s r5 t irpor internal reset timeout after por 15 - 30 ms r6 t irbor internal reset timeout after bor a a. 20 * t mosc_per 2.5 - 20 s r7 t irhwr internal reset tim eout after hardware reset ( rst pin) 15 - 30 ms r8 t irswr internal reset timeout after software-initiated system reset a 2.5 - 20 s r9 t irwdr internal reset timeout after watchdog reset a 2.5 - 20 s r10 t irldor internal reset tim eout after ldo reset a 2.5 - 20 s r11 t vddrise supply voltage (v dd ) rise time (0v-3.3v) 100 ms
lm3s817 data sheet may 4, 2007 371 preliminary figure 19-8. external reset timing (rst ) figure 19-9. power-on reset timing figure 19-10. brown-out reset timing figure 19-11. software reset timing rst /reset (internal) r7 vdd /por (internal) /reset (internal) r3 r1 r5 vdd /bor (internal) /reset (internal) r2 r4 r6 r8 sw reset /reset (internal)
electrical characteristics 372 may 4, 2007 preliminary figure 19-12. watchdog reset timing figure 19-13. ldo reset timing wdt reset (internal) /reset (internal) r9 ldo reset (internal) /reset (internal) r10
lm3s817 data sheet may 4, 2007 373 preliminary 20 package information figure 20-1. 48-pin lqfp package ccc aaa bbb ddd notes: 1. all dimensions are in mm. all dimensioning and tolerancing conform to ansi y14.5m-1982. 2. the top package body size may be smaller than the bottom package body size by as much as 0.20. 3. datums and to be determined at datum plane . 4. to be determined at seating plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 6. surface finish of the package is #24-27 charmille (1.6-2.3mr 0 ) pin 1 and ejector pin may be less than 0.1mr 0 . 7. dambar removal protrusion does not exceed 0.08. intrusion does not exceed 0.03. 8. burr does not exceed 0.08 in any direction. 9. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead is 0.07 for 0.40 and 0.50 pitch package. 10. corner radius of plastic body does not exceed 0.20. 11. these dimensions apply to the flat section of the lead between 0.10 and 0.25 from the lead tip. 12. a1 is defined as the distance from the seating plane to the lowest point of the package body. 13. finish of leads is tin plated. 14. all specifications and dimensions are subjected to ipac?s manufacturing process flow and materials. 15. the packages described in the drawing conform to jedec m5-026a. where discrepancies between the jedec and ipac documents exist, this drawing will take the precedence. a-b -d- -h- -c- symbol package type note 48ld lqfp min nom max a === === 1.60 a1 0.05 === 0.15 a2 1.35 1.40 1.45 d 9.00 bsc d1 7.00 bsc e 9.00 bsc e1 7.00 bsc l 0.45 0.80 0.75 e 0.50 bsc b 0.17 0.22 0.27 b1 0.17 0.20 0.23 c 0.09 === 0.20 c1 0.09 === 0.16 tolerances of form and position aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08
374 may 4, 2007 preliminary appendix a. serial flash loader the stellaris serial flash loader is used to down load code to the flash memory of a device without the use of a debug interface. the serial flash l oader uses a simple packet interface to provide synchronous communication with the device. the fl ash loader runs off the crystal and does not enable the pll, so its speed is determined by the crystal used. the two serial interfaces that can be used are the uart0 and ssi interfaces. fo r simplicity, both the data format and communication protocol are identi cal for both serial interfaces. 21.1 interfaces once communication with the flash loader is esta blished via one of the se rial interfaces, that interface is used until the flash lo ader is reset or new code takes over. for example, once you start communicating using the ssi port, communicati ons with the flash loader via the uart are disabled until the device is reset. 21.1.1 uart the universal asynchronous receivers/transmitte rs (uart) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. the baud rate used for communication is automatically detected by the flash loader and c an be any valid baud rate supported by the host and the device. the auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is runni ng the serial flash loader. this is actually the same as the hardware limitation for the maximum baud rate for any uart on a stellaris device. in order to determine the baud rate, the serial fl ash loader needs to determine the relationship between its own crystal frequency and the baud ra te. this is enough information for the flash loader to configure its uart to the same baud rate as the host. this automatic baud rate detection allows the host to use any va lid baud rate that it wants to communicate with the device. the method used to perform this automatic synchr onization relies on the host sending the flash loader two bytes that are both 0x55. this generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the uart to match the host?s baud rate. after the host sends the pattern, it attempts to read back one byte of data from the uart. the flash loader returns the value of 0xcc to indicate successful detection of the baud rate. if this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xcc byte again until the flash loader acknowledges that it has received a synchronizatio n pattern correctly. for example, the time to wait for data back from the flash loader should be calculated as at least 2* (20(bits/sync)/baud rate (bits/sec)). for a baud rate of 115200, this time is 2*(20/115200) or 0.35ms. 21.1.2 ssi the synchronous serial interface (ssi) port also uses a fixed serial format for communications, with the framing defined as motorola format with sph set to 1 and spo set to 1. see the section on ssi formats for more details on this transfe r protocol. like the uart, this interface has hardware requirements that limit the maximum spe ed that the ssi clock can run. this allows the ssi clock to be at most 1/12 the crystal frequency of the board running the flash loader. since the host device is the master, the ssi on the flash l oader device does not need to determine the clock as it is provided directly by the host. 21.2 packet handling all communications, with the exception of the ua rt auto-baud, are done via defined packets that are acknowledged (ack) or not acknowledged (nak) by the devices. the packets use the same
lm3s817 data sheet may 4, 2007 375 preliminary format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. 21.2.1 packet format all packets sent and received from the device use the following byte-packed format. struct { unsigned char ucsize; unsigned char ucchecksum; unsigned char data[]; }; ucsize ? the first byte received holds the total size of the transfer including the size and checksum bytes. ucchecksum ? this holds a simple checksum of the bytes in the data buffer only. the algorithm is data[0]+data[1]+?+ data[ucsize-3]. data ? this is the raw data intended for the devi ce, which is formatted in some form of command interface. there should be ucsize ? 2 bytes of data provided in this buffer to or from the device. 21.2.2 sending packets the actual bytes of the packet can be sent individually or all at once, the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. this limitation is discussed further in the commands that interact with the flash. once the packet has been formatted correctly by the host, it should be sent out over the uart or ssi interface. then the host should poll the uart or ssi interface for the first non-zero data returned from the device . the first non-zero byte will either be an ac k (0xcc) or a nak (0x33) byte from the device indicating the packet was received successfully (ack) or unsuccessfully (nak). this does not indicate that the actual cont ents of the command issued in the data portion of the packet were valid, just that th e packet was received correctly. 21.2.3 receiving packets the flash loader sends a packet of data in the sa me format that it receives a packet. the flash loader may transfer leading zero data before the fi rst actual byte of data is sent out. the first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. there is no break in the data after the first non-zero byte is sent from the flash loader. once the device communicating with the flash loader receives all the bytes, it must either ack or nak the packet to indicate that the transmissi on was successful. the appropriate response after sending a nak to the flash loader is to resend the command that failed and request the data again. if needed, the host may send leading ze ros before sending down the ack/nak signal to the flash loader, as the flash loader only accepts the first non-zero data as a valid response. this zero padding is needed by the ssi interface in order to receive data to or from the flash loader. 21.3 commands the next section defines the list of commands that c an be sent to the flash loader. the first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent.
376 may 4, 2007 preliminary 21.3.1 command_ping (0x20) this command simply accepts the command and sets the global status to success. the format of the packet is as follows: byte[0] = 0x03; byte[1] = checksum(byte[2]); byte[2] = command_ping; the ping command has 3 bytes and the value for command_ping is 0x20 and the checksum of one byte is that same byte, making byte[1] also 0x20. since the ping command has no real return status, the receipt of an ack can be interprete d as a successful ping to the flash loader. 21.3.2 command_get_status (0x23) this command returns the status of the last co mmand that was issued. typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. the command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. the last step is to ack or nak the received data so the flash loader knows that the data has been read. byte[0] = 0x03 byte[1] = checksum(byte[2]) byte[2] = command_get_status 21.3.3 command_download (0x21) this command is sent to the flas h loader to indicate where to store data and how many bytes will be sent by the command_send_data commands that follow. the command consists of two 32-bit values that are both transferred msb first. the first 32-bit value is the address to start programming data into, while the se cond is the 32-bit size of the data th at will be sent. this command also triggers an erase of the full area to be programmed so this command takes longer than other commands. this results in a longer time to receive the ack/nak back from the board. this command should be followed by a command_get_status to ensure that the program address and program size are valid for the device running the flash loader. the format of the packet to se nd this command is a follows: byte[0] = 11 byte[1] = checksum(bytes[2:10]) byte[2] = command_download byte[3] = program address [31:24] byte[4] = program address [23:16] byte[5] = program address [15:8] byte[6] = program address [7:0] byte[7] = program size [31:24] byte[8] = program size [23:16] byte[9] = program size [15:8] byte[10] = program size [7:0] 21.3.4 command_send_data (0x24) this command should only follow a command_download command or another command_send_data command if more data is needed. consecutive send data commands
lm3s817 data sheet may 4, 2007 377 preliminary automatically increment address and continue progr amming from the previous location. the caller should limit transfers of data to a maximum 8 by tes of packet data to al low the flash to program successfully and not overflow input buffers of the serial interfaces. the command terminates programming once the number of bytes indi cated by the command_download command has been received. each time this functi on is called it should be followed by a command_get_status to ensure that the data wa s successfully programmed into the flash. if the flash loader sends a nak to this command, th e flash loader does not increment the current address to allow retransmission of the previous data. byte[0] = 11 byte[1] = checksum(bytes[2:10]) byte[2] = command_send_data byte[3] = data[0] byte[4] = data[1] byte[5] = data[2] byte[6] = data[3] byte[7] = data[4] byte[8] = data[5] byte[9] = data[6] byte[10] = data[7] 21.3.5 command_run (0x22) this command is used to tell the flash loader to execute from the address passed as the parameter in this command. this command consists of a single 32-bit value that is interpreted as the address to execute. the 32-bit value is transmitted msb first and the flash loader responds with an ack signal back to the host device before actually exec uting the code at the given address. this allows the host to know that the command was received successfully and the code is now running. byte[0] = 7 byte[1] = checksum(bytes[2:6]) byte[2] = command_run byte[3] = execute address[31:24] byte[4] = execute address[23:16] byte[5] = execute address[15:8] byte[6] = execute address[7:0] 21.3.6 command_reset (0x25) this command is used to tell the flash loader device to reset. this is us eful when downloading a new image that overwrote the flash loader and wants to start from a full reset. unlike the command_run command, this allows the initial stack pointer to be read by the hardware and set up for the new code. it can also be used to rese t the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader. byte[0] = 3 byte[1] = checksum(byte[2]) byte[2] = command_reset
378 may 4, 2007 preliminary the flash loader responds with an ack signal back to the host device before actually executing the software reset to the device running the flash loader. this allows the host to know that the command was received successfu lly and the part will be reset.
lm3s817 data sheet may 4, 2007 379 preliminary ordering and contact information ordering information development kit the luminary micro stellaris? family development kit provides the hardware and software tools that engineers need to begin development quickly. ask your luminary micro distributor for part number dk-lm3s817. see the luminary micro website for the la test tools available. company information founded in 2004, luminary micro, inc. designs, ma rkets, and sells arm cortex-m3-based microcontrollers (mcus). austin, texas-based luminary micro is the lead partner for the cortex-m3 processor, delivering the world's first silicon implementation of the cortex-m3 processor. luminary mi cro's introduction of the stellaris? family of products provides 32-bit performance for the same price as current 8- and 16-bit microcontroller designs. with entry-level pricing at $1.00 for an arm technology-based mcu, luminary micro's stellaris product line allows for standardization that eliminates fu ture architectural upgrades or software tool changes. luminary micro, inc. 108 wild basin, suite 350 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www.luminarymicro.com order number features flash (kb) sram (kb) gpios a a. minimum is number of pins dedicated to gpio; additional pins ar e available if certain peripherals are not used. see data sheet for details. timers b b. one timer available as rtc. adc uart(s) ssi i 2 c analog comparator(s) pwm c c. pwm motion control functionality can be achieved through dedicated motion c ontrol hardware (using the pwm pins) or through the motion control features of the general-purpose timers (using the ccp pins). see data sheet for details. qei operating temperature d d. i=industrial (?40 to 85c). package e e. qn=48-pin rohs-compliant lqfp. speed (clock frequency in mhz) samples per second # of 10-bit channels pwm pins ccp pins lm3s817-iqn50 64 8 1 to 30 31m 62 ? 166- i qn50 lm3s817-iqn50(t) tools to begin development quickly
380 may 4, 2007 preliminary support information for support on luminary micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3

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